;
; assuming RA0 connected to resistor(s) to produce the 0.0/0.3v
; level and RB0 connected to resistor(s) to produce the 1.0v
; level.
;
; the first 2 delays would be used to stuff the 32 byte work
; buffer. The 588 cycles available in each of the 20 vertical
; sync' lines would be used for updating the video buffer.
;
frame
movlw 242 ;
movwf hctr ; set horizontal line counter
hline
bcf LATA,0 ; 00.0 usecs - set 0.0v 'sync' level
DelayCy(47) ; "sync"
bsf LATA,0 ; 04.7 usecs - set 0.3v 'blk' level
DelayCy(57) ; "back porch"
B00 movf POSTINC0,W ;
movwf LATB ; 10.6 usecs
nop ;
rrcf LATB,F ; 10.8 usecs
nop ;
rrcf LATB,F ; 11.0 usecs
nop ;
rrcf LATB,F ; 11.2 usecs
nop ;
rrcf LATB,F ; 11.4 usecs
nop ;
rrcf LATB,F ; 11.6 usecs
nop ;
rrcf LATB,F ; 11.8 usecs
nop ;
rrcf LATB,F ; 12.0 usecs
;~~~~~~~
B01..B30 ; same code for bytes 01..30
;~~~~~~~
B31 movf POSTINC0,W ;
movwf LATB ; 60.2 usecs
nop ;
rrcf LATB,F ; 60.4 usecs
nop ;
rrcf LATB,F ; 60.6 usecs
nop ;
rrcf LATB,F ; 60.8 usecs
nop ;
rrcf LATB,F ; 61.0 usecs
nop ;
rrcf LATB,F ; 61.2 usecs
nop ;
rrcf LATB,F ; 61.4 usecs
nop ;
rrcf LATB,F ; 61.6 usecs
;~~~~~~~
nop ; 61.7 usecs
nop ; 61.8 usecs
movlw 20 ; 61.9 usecs
movwf vctr ; 62.0 usecs
clrf LATB ; 62.1 usecs - set 0.3v 'blk' level
DelayCy(14-3) ; "front porch"
decfsz hctr,F ; 63.2 usecs - 242 lines?
bra hline ; 63.3 usecs
nop ; 63.4 usecs
vsyn1
bsf LATA,0 ; set 0.3v level
DelayCy(47-1) ; inverted "sync"
bcf LATA,0 ; set 0.0v level
DelayCy(588-4) ;
decfsz vctr,F ; all 20 vsync lines?
bra vsyn1 ; no, branch, else
;
; the vsyn1 code needs to be modified to jump to "frame" (a
; new frame) with the correct timing...
;