Phase looped loop on DCF77 timing signal

[eblc1388]

Phase locked loop on DCF77 timing pulses

I have bought a radio clock that has a DCF77 receiver module receiving timing signal at 77.5KHz.

I would like to phase lock to the DCF77 timing signal pulse, which occurs every second except on the 59th second where it is suppressed to indicate the arrival of the next minute.

The timing pulse itself is not a square wave in nature, having width of 0.1 or 0.2 second depends on the timing data.

The problem arises from the missing input pulse during the 59th second as it will surely create a very large error signal in the phase comparator and offset the VCO output frequency considerably.

Any idea or suggestion on how to tackle the situation? A counter+analog switch to disable the error input to the filter capacitor after 58 counts, a "fake" pulse taken from the phase locked output to replace the input to fool the PLL or....

 

[Roff]

I like the idea of putting a hold on the loop error voltage, but if you are using a phase/frequency detector (PFD), the detector will still get screwed up by the missing pulse (it always needs to see a one-for-one correspondence on the two inputs). If you are going to count to 58, it might be better to knock out the next pulse into the PFD (the one from the VCO frequency divider). That way, the frequency detection will still be correct, and the error voltage will automatically hold.

 

[Sceadwian]

Google "555 Missing pulse detector"
The 555 will generate a pulse for you if the 'time out' period expires, so that one pulse would be an R/C timed pulse the rest would be from your time base, simply select a decently temperature stable resistor and capacitor. Even that isn't critical since all you're trying to do is approximatly replace the missing pulse to avoid gross error.

 

[eblc1388]

Thanks for your inputs, gentlemen.

If I use a missing pulse detector, I would have to set a longer period for the detector to trigger in normal situation. This trigger point also has to be wider than the lock in range of the VCO for it not to operate prematurely.

I'll try Roff's suggestion of removing the pulse from the frequency divider output to the phase/freq comparator(I'm using edge triggered mode instead of 90 degree when in lock). This would mean the capacitor should be holding charge for two seconds instead of one during this period. Its voltage could droop more but I can use an opamp follower in between.

Just wonder what effect it will have if I fake the input pulse using the output pulse during that 59th second period. Assuming the PLL has already been in locked mode before the coming of the 59th second. Would it be better for the overall loop performance with less disturbance to the filtering capacitor?

I can easily do either using a PIC to sample the timing data and know well before hand that the 59th second is coming.

 

[Roff]

Thanks for your inputs, gentlemen.

If I use a missing pulse detector, I would have to set a longer period for the detector to trigger in normal situation. This trigger point also has to be wider than the lock in range of the VCO for it not to operate prematurely.

I'll try Roff's suggestion of removing the pulse from the frequency divider output to the phase/freq comparator(I'm using edge triggered mode instead of 90 degree when in lock). This would mean the capacitor should be holding charge for two seconds instead of one during this period. Its voltage could droop more but I can use an opamp follower in between.

Just wonder what effect it will have if I fake the input pulse using the output pulse during that 59th second period. Assuming the PLL has already been in locked mode before the coming of the 59th second. Would it be better for the overall loop performance with less disturbance to the filtering capacitor?

I can easily do either using a PIC to sample the timing data and know well before hand that the 59th second is coming.

Can you even get the loop to lock with the missing pulse? If you are using a 4046, I don't think the PFD will allow it. Maybe you could initiate lock using the missing pulse detector, then switch to the fake pulse after the loop is locked.

 

[eblc1388]

I don't understand why would the loop not lock when there are 59 seconds before/after the arrival of the "fake" missing pulse? All these 59 pulses are properly timed and 59 seconds is a long long time.

My idea is to provide the "fake" missing 59th pulse from the frequency divider output regardless whether the loop is locked or not, in the hope that locking will be achieved some seconds later after this "fake" pulse and remain locked until the arrival of the next 59th second pulse.

My logic works like this. I will first monitor the timing pulses and pick up where there is a two second gap between pulses to establish an initial counting reference. From then on I wait for 58 more pulses(hoping that the PLL VCO will be locked by then) and swap in the output pulse to fake the 59th pulse for a 0.5 second duration.

 

[Roff]

That sounds good. Please keep us posted on your progress (or lack thereof).