Thanks for your inputs, gentlemen.
If I use a missing pulse detector, I would have to set a longer period for the detector to trigger in normal situation. This trigger point also has to be wider than the lock in range of the VCO for it not to operate prematurely.
I'll try Roff's suggestion of removing the pulse from the frequency divider output to the phase/freq comparator(I'm using edge triggered mode instead of 90 degree when in lock). This would mean the capacitor should be holding charge for two seconds instead of one during this period. Its voltage could droop more but I can use an opamp follower in between.
Just wonder what effect it will have if I fake the input pulse using the output pulse during that 59th second period. Assuming the PLL has already been in locked mode before the coming of the 59th second. Would it be better for the overall loop performance with less disturbance to the filtering capacitor?
I can easily do either using a PIC to sample the timing data and know well before hand that the 59th second is coming.