PIC16F628A and AT28C256

[moahrs]

Hi all,

I am a problem very very stranger.

I am make a circuit using old processor, for educational proposite, and all works fine, since cpu up to programmer (using PIC16F628A and serial port).

In a SRAM, 62256, all works fine, the programmer is working very fine.

Then I buyed one AT28C256, EEPROM 32K x 8. I read the datasheet, programed code in 16F628A, and worked very fine, but something was "erasing" or "modifing" the Bytes in EEPROM. The I read in datasheet wich the SDP ("Software Protection") on this model is in default "disabled" in manufacture.

Then, I sending the 3 codes to enable the SDP, and VOILA, I cant write anymore in this EEPROM. I LOVED THIS.

I try to send the 6 Bytes to disable SDP again, and nothing. I try to send 3 bytes to disable the SDP, write the 64 Bytes, and in teory, then SDP enable again after, but nothing is disabling the SDP. I cant write again at any adress.

Any1 can helpme ? I expend all my weekend to solve this and nothing.

PS: Since in datasheet is write "like a SRAM", I suposed wich I dont need erase this EEPROM with 12v or with other software in EEPROM ("like program to erase entire chip").



Ty a lot.
Moacir Jr.

 

[ericgibbs]

hi,
You should be able to unlock by using the attached sequence
.

 

[Pommie]

Are you sending 3 or 6 bytes to unprotect? It should be 6 to turn off protection, 3 to write up to 64 bytes.
Are you respecting the 64 byte boundaries?
Are you polling to see when the write has completed?
Is your supply over 3.8V.

Mike.

 

[moahrs]

Hi, ty for response.

Yeah, I am try using both sequences, but anyone not work, the memory just locked to write. Read is normal.

Exist some sequence to reset or anythink like this ?

The 16F628A is processing in 4MHZ (internal clock) and time, for example, 150us between each command sequence or byte (1 to 64), is OK, i am not exceeding this time. Before I send 3 codes to enable SDP, the memory worked very well.



Ty
Moacir Jr.

 

[moahrs]

Hi pommie,

I verified, and the suply is over 3.8v.

Yes, I try sending 6 bytes before begins sending packets of the 64 bytes up to end, and try sending 3 bytes after send each 64 bytes.

I verifing the pooling, I was verifyng the complement of IO7 of last byte writed.

I do not believe wich I was damaged this chip.

What i do to enable SDP:

- How I sayed, the chip was manufactured with SDP disabled.
- Then, after I writing all bytes, in the final of my program, I sending the 3 bytes of the SDO and more nothing (anyone byte).
- After this, the SDP was enabled, but how I sayed, I cant disbled this now.


Ty a lot.
Moacir Jr.

 

[moahrs]

Ty for all.. Problem solved. In the pic, the time for send commando to AT28C256 was wrong (more than 50us).

I reprogram, and now works very well.


Moacir Jr.

 

[eric_esterlingot]

well, what do you mean by wrong command timing ?
I trying to write in a at28c256, and seems something is wrong, i follow the datasheet waveform, but the memory does not record anything...

 

[Pommie]

Can you read the chip?
For writing,
is /we low?
is /ce low?
is /oe high?
is software protection turned off?

Mike.

 

[eric_esterlingot]

That's what i've done...

My memories are ATMEL AT28C256-15PI, SDP "should be" off...
Whatever, i tried to use the 6 bytes SDP disable algorithm from the datasheet (just in case)... Without any result.
What intrigate me is the send command time, I didn't find any information about it.
MOAHRS says its was wrong : "(more than 50 usec)"...
Do the SDP disabled sequence (or any other command sequence) have a special time limit (min or max) ?

My actual writing sequence is:

1) OE is high, Adress bus is stable => Set byte on data bus
2) wait for 1 usec
3) CE goes low
4) wait 1 usec
5) WE goes low
6) wait for 30 usec
7) WE goes high
8) wait for 1 usec
9) CE goes high
10) wait for 4 msec
try to read... and result is FF... allways

In the first place, I tried to poll Data7, and never get out off loop, so i decided to wait the 4 msec delay...
I test with 5 new chips... and allways the same result...

 

[Pommie]

Are you sure your read routine is working? Do you have a chip with some data to test your read routine?

Mike.

 

[eric_esterlingot]

Well, using a RAM 62256, it works fine...
the read routin is:

1) WE, OE, CE is high, Adress bus is stable
2) CE goes low
3) wait for 1 usec
4) OE goes low
5) wait for 30 usec
6) read the data bus (=> FF allways)
7) OE goes high
8) CE goes high

and result is FF... allways

 

[Jon Wilder]

Due to the low pin count of a 16F628A, a couple of questions -

Are you time multiplexing read/write with an external latch? If so, how do you have enough pins to drive the LE pin on the latch? Let alone the /CE /WE /RD pins? If not, are you interfacing D0-D7 to one port on the PIC while only driving A0-A7 on the other port? Again how would you have enough pins left to drive /CE /WE /RD? And only driving A0-A7 you would only be able to access the lower 0x00-0xFF range of addresses, which the PIC's on chip EEPROM could handle by itself.

Or are you using one port on the PIC for address high/address low/data and latching all 3 of these in time multiplex fashion?

There are 15 address pins on that chip. If you don't have enough to drive the address pins, you cannot use the full range of available memory space, in which you should ask yourself why you're using such a large memory chip for such a small uC. These parallel EEPROM's were meant for processors with external address/data buses on chip such as the 8051.

I would recommend an SPI serial EEPROM such as the 25LC256. The SPI protocol is super easy to bit bang in assembly with the F628A and the memory chip would only require a minimum of 4 pins from the F628A to drive it (WP and /HOLD are optional).