PIC18F - Updating CCPR1 avoiding unexpected interrupt

[atferrari]

Micro family 18F

Module CCP1 in compare mode against TMR1 in timer mode.

Setting: "toggle output pin (RC2) on match condition".

My application currently loads alternatively CCPR1H:L with HALF_T1 and HALF_T2 and restarts TMR1. (It works OK like that).

Trying to follow the frequent advice received, to leave TMR1 running alone and ADDING the next value to CCPR1H:L, here is my question:

How to add the low and high bytes of next HALF_Tx, without risking to have an undesired match BEFORE both are added? In extreme cases this actually WOULD happen in my application. Tested.

For other settings I know how to do it (changing CCP1M0) but no for "toggle on match". Any change of a single bit from CCP1M3:CCP1M0 would enter in an undesired condition, so I discarded that.

I find this problem mentioned somewhere but no solution explained for this case.

I want to retain the "toggle on match" setting.

Help appreciated.

 

[Pommie]

The problem can be fixed by altering the order that things are done. When you add to CCPR an interrupt may be generated and so you have to make sure that this spurious interrupt doesn't cause a problem. If you have not changed the direction of the output pulse then the spurious interrupt will not have any effect.

The order things should be done is,
Write to CCPRL/H.
Toggle CCP1M0.
Clear CCP1IF.

Mike.

 

[atferrari]

Sorry Pommie; from my orginal post:

I want to retain the "toggle on match" setting.

I will keep trying and post the outcome even if takes me long time.

 

[Pommie]

Sorry, I should have read your original post more carefully. I don't understand why you want to keep the toggle on match setting but as you do, can you simply decrement the high byte before writing low then high of CCPRL/H. This should eliminate any spurious matches.

Mike.