donniedj
Banned
The 24FJ family does not have EEPROM, like many of the upcoming chips, and instead permits Flash Program memory to be written at run time a.k.a. Run-Time Self-Programming (RTSP). RTSP is not new for PICs but mandatory large blocks of erasing is new and annoying.
Well the flash is erased in blocks of 1536 bytes or 512 x 3 byte words. Not just erased buy must be and is automatically erased in 1536 byte segments of which will be referred to as 0x0400 walls. A word is 3 bytes but a word only consumes 2 address locations so 0x0400 /2 = 0x0200 which equals 512 (3byte) words. Confusing? you don't know the half of it
So if one needs to change a couple of bytes say 6 addressed as 0x000700 and 0x000702, 24-bit words here, first that wall of flash "should" be copied. before erasing:
- Changing 0x0700 and 0x0702
- Erases block 0x0400 to 0x0800
- Changing 0x0C02 and 0x0D00
- Erases block 0x0C00 to 0x1000
Second, an erase is performed clearing the blocks above. Then our 2 target addresses changed. After which, the entire 0x000400 to 0x000800 is re-flashed back else only the 2 target address well be saved and everything else in that 0x0400 wall space will be erased. The 0x0400 wall is composed of 8 rows and each row must be flashed which consumes 3 milliseconds max. Thats 24 millseconds max, not including reading 512 words and writing 512 words, just to modify 2 locations in flash.
Four Questions:
1. Is this not wasteful? Regular EEPROM is a byte by byte operations and is slow for large chunks of data. Yet EEPROM is not used for large chunks hence is relatively fast.
2. A lot can happen in the process of reading 512 words, modifying a few and re-flashing 512 words. That data may need to be accessed only to be denied because is was erased and the re-flashing is still in process.
3. This goes against every thing that is electronics. Waste nothing, spend not a nanosecond of useless time away from what is important, brief, brevity, and so on and so forth... There is a reason for not placing 100 ohm resistors across random +V to ground terminals. There is a reason why the coupling caps and crystals are positioned as close as possible to where its needed. There is a reason why LDO regulators exist and their predecessors are the things that should not have been. Why must I occupy such a huge number of clock cycles to change a few locations in flash. The other family of PICs allow you to directly write to flash without such a large overhead. If you are not so incredibly careful you can all to easy wipe out main line code (remember the 0x0400 wall) without even knowing it. Why has the indirect addressing for the 24F family been given steroids along with all the other powerful instructions? To increase throughput perhaps or to reduce the number of instructions to accomplish a task perhaps. Like the rest of planet earth, to progress forward? So why is there no single word or smaller controllable block method of flash erasing and re-flashing? Who is the clueless stupid jackle upper management or the singular self audience suave grandeur idiot to blame?
4. Was the 512 word block erase RTSP truly meant exclusively for Boot Loading? The very name RTSP suggest the effectiveness is optimized only for Boot Loading. Self-Programming is not an efficient means to implement EEPROM. Too much overhead, too much can go wrong during flashing such a huger area of memory, and way to damn easy to kill your own code.
I know there are tricks to this game. Store my re-writable data at the bottom of a 0x0400 wall and just re-flash a small portion. Keep all re-writable data far far far away from main line code tucked down deep in the dark recesses of program memory. Nice tricks but this is not a circus or best in show. I need to use the program flash to replace external I2C EEPROM for reduced component count, cost, and speed. I need to use every drop of that precious program flash memory like a leaky canteen in a desert. Has anyone here used the 24F family re-writable flash effectively? I mean that as not as documented? Or am I using the flash erase incorrectly?
Well the flash is erased in blocks of 1536 bytes or 512 x 3 byte words. Not just erased buy must be and is automatically erased in 1536 byte segments of which will be referred to as 0x0400 walls. A word is 3 bytes but a word only consumes 2 address locations so 0x0400 /2 = 0x0200 which equals 512 (3byte) words. Confusing? you don't know the half of it
So if one needs to change a couple of bytes say 6 addressed as 0x000700 and 0x000702, 24-bit words here, first that wall of flash "should" be copied. before erasing:
- Changing 0x0700 and 0x0702
- Erases block 0x0400 to 0x0800
- Changing 0x0C02 and 0x0D00
- Erases block 0x0C00 to 0x1000
Second, an erase is performed clearing the blocks above. Then our 2 target addresses changed. After which, the entire 0x000400 to 0x000800 is re-flashed back else only the 2 target address well be saved and everything else in that 0x0400 wall space will be erased. The 0x0400 wall is composed of 8 rows and each row must be flashed which consumes 3 milliseconds max. Thats 24 millseconds max, not including reading 512 words and writing 512 words, just to modify 2 locations in flash.
Four Questions:
1. Is this not wasteful? Regular EEPROM is a byte by byte operations and is slow for large chunks of data. Yet EEPROM is not used for large chunks hence is relatively fast.
2. A lot can happen in the process of reading 512 words, modifying a few and re-flashing 512 words. That data may need to be accessed only to be denied because is was erased and the re-flashing is still in process.
3. This goes against every thing that is electronics. Waste nothing, spend not a nanosecond of useless time away from what is important, brief, brevity, and so on and so forth... There is a reason for not placing 100 ohm resistors across random +V to ground terminals. There is a reason why the coupling caps and crystals are positioned as close as possible to where its needed. There is a reason why LDO regulators exist and their predecessors are the things that should not have been. Why must I occupy such a huge number of clock cycles to change a few locations in flash. The other family of PICs allow you to directly write to flash without such a large overhead. If you are not so incredibly careful you can all to easy wipe out main line code (remember the 0x0400 wall) without even knowing it. Why has the indirect addressing for the 24F family been given steroids along with all the other powerful instructions? To increase throughput perhaps or to reduce the number of instructions to accomplish a task perhaps. Like the rest of planet earth, to progress forward? So why is there no single word or smaller controllable block method of flash erasing and re-flashing? Who is the clueless stupid jackle upper management or the singular self audience suave grandeur idiot to blame?
4. Was the 512 word block erase RTSP truly meant exclusively for Boot Loading? The very name RTSP suggest the effectiveness is optimized only for Boot Loading. Self-Programming is not an efficient means to implement EEPROM. Too much overhead, too much can go wrong during flashing such a huger area of memory, and way to damn easy to kill your own code.
I know there are tricks to this game. Store my re-writable data at the bottom of a 0x0400 wall and just re-flash a small portion. Keep all re-writable data far far far away from main line code tucked down deep in the dark recesses of program memory. Nice tricks but this is not a circus or best in show. I need to use the program flash to replace external I2C EEPROM for reduced component count, cost, and speed. I need to use every drop of that precious program flash memory like a leaky canteen in a desert. Has anyone here used the 24F family re-writable flash effectively? I mean that as not as documented? Or am I using the flash erase incorrectly?
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