Please explain LIN Parameter, bit quantization.

We are using number of Local Interconnect Network(LIN) channels from Renesas RH850 / U2A16 Microcontroller in our embedded system. All LIN channels in our embedded system are Master.

What is LIN Parameter called bit quantization? I didn't find explanation of this parameter in LIN Controller user's manual.

I don't know if it applies to LIN, but in CAN communication, the bit time is divided into several time quanta (Tq).

In almost all serial communication, the time taken for one bit has to be further divided. When receiving, after the first edge of a frame has been received, the bits should be sampled about half-way through each bit. So that the receiver can decide when to sample the data, it will have to have a clock that runs faster than the bit rate.

In CAN systems, the bit period is divided into several sections, and each section is a whole number of Tq long. The point within the bit time where the data is sampled can be adjusted by adjusting the number of Tq times before and after the sampling.

I've not seen that done with LIN, but the same principles apply. The UARTS that I have used for LIN have clock rates that are a lot higher than the Baud rate, and the UART will read the bit somewhere near the middle of the bit time.

Bit quantization is normally applied to binary. This is an ILLUSTRATION not using real numbers.
Lets say our fictitious converter represents 0-100 and each bit represents 1 increment. NOT POSSIBLE in real life.
The spec says +1 bit. A number such as "1" is one bit and therefore it's value us known by +-50%, On the other hand 99 +-1 bit is more like a 1% error. The error depends on how far full scale you are.

This is my own explanation.

Real world mode:

0-4095 is likes a 12 bit converter. At the low end +-1 bit the quantization error (1 bit) is higher. The error in % depends on the magnitude of the number measured.

So, 1-5V signals are better that 0-5 V signals for accuracy.

>> In CAN systems, the bit period is divided into several sections, and each section is a whole number of Tq long.
Is each section programmed by CAN Driver?

>> The point within the bit time where the data is sampled can be adjusted by adjusting the number of Tq times before and after the sampling.
Are the adjustment values fetched from CAN Controller registers?

>> I've not seen that done with LIN, but the same principles apply.
Attached is section 2.4 from Renesas RH850 LIN Controller Application Note. One of the parameters in section 2.4 is Number of segments (quanta). Are these segments determined by LIN controller? LIN driver doesn't need to program time quanta whole number(s) ?

jani12 said:

>> In CAN systems, the bit period is divided into several sections, and each section is a whole number of Tq long.
Is each section programmed by CAN Driver?

>> The point within the bit time where the data is sampled can be adjusted by adjusting the number of Tq times before and after the sampling.
Are the adjustment values fetched from CAN Controller registers?

>> I've not seen that done with LIN, but the same principles apply.
Attached is section 2.4 from Renesas RH850 LIN Controller Application Note. One of the parameters in section 2.4 is Number of segments (quanta). Are these segments determined by LIN controller? LIN driver doesn't need to program time quanta whole number(s) ?

Click to expand...

A lot of what I know about Tq in CAN drivers has come from Microchip. Here is one of their data sheets:- https://ww1.microchip.com/downloads/en/DeviceDoc/70353C.pdf

Section 21.9 of that explains bit timing. The length of each section is defined in the CAN configuration registers.

I think that you would always have to have a whole number of Tq or segments in one bit. I can't see how it could work with fractional numbers.

On the CAN microcontroller that I have used, there is a PLL that allows a wide range of frequency options, so the LIN or CAN baud rate does not have to be an integral fraction of the oscillator speed. However the CAN and LIN Baud rates do have to be obtained by dividing the PLL output frequency by a whole number. With modern processors, and for the slow speeds that LIN runs at, the divide ratios needed are large numbers, and that gives a lot of flexibility.

For instance, if the processor is running at 50 MHz, and the LIN is at 19200 Baud, the divide needed is 2604.1666 so it's not possible to have exactly the right divide ratio. However, dividing by 2600 will only be 0.16% in error, which is fine for LIN.

With lower frequency clock speed, and less flexibility in the divide ratio, getting the correct speed was more problem with older processors. For instance, if the processor is running at 8 MHz, and can only divide by powers of 2, the correct divide ratio would be 416.6666. If the only ratios available were 128, 256, 512 1024 etc then none of those would be close enough to work and different clock speed would have to be chosen.