vinodquilon Member Mar 19, 2010 #1 I am using PLL for clock recovery (see attachment). PLL 565 CLOCK RECOVERY (bit sync.) What are the design criterion s for R1,C1,R2, and C4 ? R2 and C4 determines free-running frequency of PLL. What would be the selection for c2, which determines capture range ? Does there any restriction on VCC selection as it affects lock range ? Here I am using XOR to ensure frequent data transitions. That is to avoid Consecutive Identical Digit (CID). I am using this circuit in wireless communication to recover clock from received data for bit synchronization. Attachments clock..pdf 15.5 KB · Views: 353
I am using PLL for clock recovery (see attachment). PLL 565 CLOCK RECOVERY (bit sync.) What are the design criterion s for R1,C1,R2, and C4 ? R2 and C4 determines free-running frequency of PLL. What would be the selection for c2, which determines capture range ? Does there any restriction on VCC selection as it affects lock range ? Here I am using XOR to ensure frequent data transitions. That is to avoid Consecutive Identical Digit (CID). I am using this circuit in wireless communication to recover clock from received data for bit synchronization.
vinodquilon Member Mar 19, 2010 #2 4046 over 565 Does there any advantage in using pll IC 4046 over 565 ?
vinodquilon Member Mar 19, 2010 #3 Simple Solution !!! I think R1 & C1 should design to provide one bit delay time. R2 & C4 (VCO reference clock) should be tuned to lock at transmitter data rate. I am choosing C2= 10uF, VCC= 5V.
Simple Solution !!! I think R1 & C1 should design to provide one bit delay time. R2 & C4 (VCO reference clock) should be tuned to lock at transmitter data rate. I am choosing C2= 10uF, VCC= 5V.
Hero999 Banned Mar 20, 2010 #4 I've never done this before, indeed, I didn't know it's possible to do this with a PLL. I thought the NE565 was obsolete? So the advantages of using a CD4046 is it's still made so will be easier to get hold of. Also being CMOS means it will consume less power.
I've never done this before, indeed, I didn't know it's possible to do this with a PLL. I thought the NE565 was obsolete? So the advantages of using a CD4046 is it's still made so will be easier to get hold of. Also being CMOS means it will consume less power.