poles and zeros of Laplace transform

Something most Design Engineers should know is how to do is a Sensitivity Analysis. dx/dy where x is the change in input parameter and y is the output.

This defines overall design tolerance based on input tolerance and the sum is a tolerance stackup.

Monte Carlo is then used when a complex hundreds of variables exist.

Tony Stewart said:

Something most Design Engineers should know is how to do is a Sensitivity Analysis. dx/dy where x is the change in input parameter and y is the output.

This defines overall design tolerance based on input tolerance and the sum is a tolerance stackup.

Monte Carlo is then used when a complex hundreds of variables exist.

Click to expand...

Hi there Tony,

I think you meant dy/dx ? (Let me know and i'll remove this line).

I agree, this is a very good thing to know, if not downright necessary.
Long time ago, we had a resistor value sensitivity issue that went overlooked for several years. If the value changed by a little more than usual, some $500 USD transistors would blow up. Back then high powered transistors were more than $100 each.

Of course out/in...thanks Al ....Murphy's corollary of inversion... If anything can be inverted, it will unless you triple check.

Yes, mismatched Rce(sat) with Rjc differences as well causes causes Shockley effect and thermal runaway.

I have figured out these sensitivities and tolerances to guarantee "no runaway criteria " for power LEDs in parallel and how much Rs to add is sufficient for mismatched diodes. If thermal mismatch is less than electrical mismatch, it stable. The point of instability is a less than infinite time constant. The safety margin for aging must be at least -10-15 dB just like gain margin in op amps. Where the thermal/ESR ratio is the gain margin. Margin drops with the square of current peaks over design limit.or rise in ambient temp.

With this margin at worst case env, , Then long happy life.

Unless bombarded unequally by gamma rays ESD etc.or similar unknown disturbance

Also for fast CMOS, the protection must be faster than the device as discharge avalanche rise time is known to be 10 ps worst case, due to L/R which is beyond possible internal protection without added L, resulting in crystalline fatigue and rise in ESR.