Your gnd error is most likely from the substrate connection in the right nmos transistor. The left nmos is connected to gnd properly, but the right one is going through the inductor. That can cause all kinds of problems by injecting noise into the substrate causing latchup. The pmos transistors are probably giving related errors, but can probably be fixed if you tie the NWELL properly. IOW both pmos transistors must be in a separate NWELL and spacing rules apply because the NWELL's are considered at different potentials. It's hard to tell in the layout the detail of the transistor structures. The inductors look ok as far as their A&B terminal but as far as their ground terminal, you might have a similar problem with them as the transistors. Depending on the inductor model used, they may need to sit in their own NWELL and have the NWELL properly tied to GND or VDD. One last thing ... I don't see any guard rings in your design. To prevent the guard rings from coupling into your coil as a parasitic secondary coil you can create a "notch" where the guard ring does not complete a circuit. Without guard rings, you can have mutual parasitic inductance between your coils. Guard rings can help minimize this. Another way to minimize mutual parasitic inductance is to design your inductors as a serpentine or interdigitated style.