problems with a miso line in spi comunication

First! the master controls the speed with the clock line ergo, the end device must be configure as a master as well.. This cannot continue for long as the clk line is in contention.

As you haven't given any details to any of the devices, I very much doubt we can help you resolve this

Recently had a big debug session with a FRAM (2mb) and a dsPIC33EV256GM304 , This SPI needs careful coding, ( I dont use any library or code help ) my problem seemed to be centered round high impedance on the MISO during the masters MOSI bytes. I had let it float , thought about pull down or up, in the end I just read the SPIBUF and put byte in a 'waste' uint8_t. .. l had to send 3 bytes address , then a dummy byte so the Fram could send its data . Probably not much help.

Firts of all, thanks for all quickly responses...

Ian, my mcu (master device), is a MSP432P401R from texas instruments, and I use the B0 module, the comunications pins are P1.5-SCLK; P1.6-MOSI;P1.7-MISO;and P5.0-CS.
The slave device is ads1292R from texas intruments too.
I have configure the spi from my master device to comunicate with a 3-pin SPI mode device.

Straight rom datasheet

datasheet said:

NOTE: Pullups can be used to avoid unnecessary toggles on the QSSI pins, which can take theslave to a wrong state. In addition, if the SSIClk signal is programmed to steady state highthrough the SPO bit in the SSICR0 register, then software must also configure the GPIO portpin corresponding to the SSInClk signal as a pullup in the GPIO Pullup Select (GPIOPUR)register.

Click to expand...

these devices are special as they have Quad SSI modules... Make sure that IF!!! I say if as I don't know, that the ssi clock isn't different between channels..

Ian, I can't find the information you shared with me. Are you sure this information is for the MSP432P401R board. Even so, I tried to make some changes to the SPI pins, such as adding pullups to try to guide the pins to the correct state, but to no avail.