#include <msp432.h>
#include "spi.h"
#include "ads1292r.h"
void set_spi(void) {
initialize_ports();
initialize_spi();
}
void initialize_spi(void) {
EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SWRST; /*EUSCI_B0 INTO RESET MODE*/
EUSCI_B0->CTLW0 = EUSCI_B_CTLW0_SWRST /*KEEP IN RESET*/
| EUSCI_B_CTLW0_MSB /*MSBIT FIRST*/
| EUSCI_B_CTLW0_SYNC /*SYNCHRONOUSE MODE(SPI)*/
| EUSCI_B_CTLW0_MST /*MASTER MODE DEVICE*/
| EUSCI_B_CTLW0_MODE_0 /*SPI 3 PIN MASTER MODE*/
| EUSCI_B_CTLW0_SSEL__SMCLK /*CLOCK SOURCE(SMCLK)*/
| EUSCI_B_CTLW0_CKPH; /*CKPL = 0; CKPH = 1*/
/*SET CLOCK DIVIDER (ASSUME SMCLK = 12MHz/24, SPI CLOCK 500KHz)*/
EUSCI_B0->BRW = 24; /*CLOCK PRESCALER (12MHz/24 = 500 KHZ)*/
/*SELECT THE PRIMARY MOCULE FUNCTION*/
/*INITIALIZE PORT REGISTERS, CONFIGURE FOR SPI FUNCTIONALITY*/
/*P1.5 (SCLK), P1.6 (MOSI), P1.7 (MISO)*/
P1->SEL0 |= BIT5 | BIT6 | BIT7; /*SELECT FIRST AND PRIMARY FUNCTION*/
P1->SEL1 &=~(BIT5 | BIT6 | BIT7); /*CONFIRM THE SEL1 IS CLEARED TO USE THE PRIMARY FUNCTION*/
P1->DIR |= BIT5 | BIT6; /*SET THIS PINS LIKE OUTPUT PIN'S*/
P1->DIR &= ~(BIT7); /*SET P1.7 LIKE A INPUT PIN*/
EUSCI_B0->CTLW0 &= ~(EUSCI_B_CTLW0_SWRST); /*RELEASE EUSCI FROM RESET*/
// EUSCI_B0->IE |= EUSCI_B_IE_RXIE;
/*IN THE ADS1292R TECHICAL DATED SBAS502C – DECEMBER 2011 – REVISED APRIL 2020 DOCUMENT, THERE IS
* A NOTE WHERE IS DEFINED THE STATUS OF SPI CLOCK SETTINGS ARE CPOL=0 AND CPHA=1.*/
}
void initialize_ports(void) {
/*P2.4 - CLK_SEL*/
/*P2.5 - START*/
/*P2.6 - POWER/RESET*/
/*P5.0 - CS*/
/* GPIO PINS ADS COMMAND PIN'S I/O */
P2->DIR |= BIT5 | BIT6 | BIT4; /* START, RESET AND CLK PIN OUTPUT */
P2->OUT &= ~(BIT5 | BIT6); /* START AND RESET PINS LOW STATE */
P2->OUT |= BIT6 | BIT4; /* CLK AND RESET PINS TO HIGH STATE*/
P5->SEL0 |= BIT0;
P5->SEL1 &= ~(BIT0);
P5->DIR |= BIT0; /*SET P5.0 CS SELECT OUTPUT */
P5->OUT |= BIT0; /*SET P5.0 CS SELECT OUTPUT */
}