Problems with CPLD programmer

Success

Congrats! Not sure why the original circuit didn't work for you, sounds like your modified version works fine (If I can locate my Xilinx DLC5 pp cable, I'll pop the cover and compare the circuit to the one posted at the Xilinx site. Pretty sure it's the same thing). Check the site I mentioned in the other thread for ideas on implementing unweighted addition, if you want to reduce your overall system clock speed. The simplest thing would be to construct one long shift register, as noted earlier.

Claude,

Just wanted to let you know that I removed all the addtional resistors - the ones across the i/o of the 74hc125s acting as schmitt triggers, and the weak pull-ups on all jtag lines. The circuit is still performing normally with the software. This means that the problem was the power supply - good call!

As for the actual project - I think I'm going to do just that, build one very long shift register, which seems quite easy from all the VHDL I've seen so far. I'll reread the unweighted-addition link you've posted again; will experiment with this approach too...but, as exams are coming up soon, I'm going to try to finish my pet project with whatever works first

Let me know if you ever find that cable.
Will be back for more vhdl questions later

Thanks again!
Avital

Hi again,

Claude:

I got my hands on an old scope - a Kenwood CS-1021 dual trace. This one is obviously diff. than the one we have at uni, which is basically a computer with some unknown hardware interface. Also, after I posted my last comment, I decided to try to "clean up" the circuit and place it in a proper container and such. Anyway, the circuit does not work again. I can't seem to adjust the scope to detect the output of the clock (using the "debug chain" feature of the iMPACT software from Xilinx). Was wondering if you could suggest the proper settings...

Thank you,
Avital