dramrattan
Member
A program with 6 assembly instructions has to be executed on an 8 bit pipelined CPU. The CPU has a 6 bytes instruction pre-fetch Queue, which fetches the instructions and fills the pipeline
1] What would happen if the 5th instruction in the program is an unconditional jump / branch ?
2] Can the number of address lines for the CPUs be determined?
1] What would happen if the 5th instruction in the program is an unconditional jump / branch ?
2] Can the number of address lines for the CPUs be determined?