pspice simulation of sample and hold circuit help!

divk1991

New Member
Hi!
I have created spice schematics circuit of a sample and hold circuit consisting of 2opamps, n-channel MOSFET, and two voltage sources. The output doesnt resemble samplen hold. I have attatched the .png files of the circuit and simulation. Please help!
Thanks!
 

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hi,
The IRF150 is a 40Amp high power MOSFET, look at the datasheet and check the die capacitances, it totally unsuitable.
Those spikes are due to the MOSFET switching capacitances.

Select a faster, low power FET.
 
That's part of the answer. Another problem is that the non-inverting inputs of the op-amps need a bias current. Connect each pin 3 to ground via a respective bias resistor (say 330k), connect U1 pin3 to V3 via a series resistor (say 1k), and connect U2 pin3 to C2 via a series resistor (say 1k).
 
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Those inputs don't need resistors. The get all the bias current they require through their connections. Why do you think there should be resistors? The inputs just need a DC path for the input bias current, which they all have.
 
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