Pulse in negative and positive transition

leonel

New Member
I need help to do a circuit that makes the follwing:
in the positive and in the negative transition i want to make a pulse and then stays off (see figure).
How i do that?
It seems simple but i can´t do that...
 

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Signal into one input of an exclusive OR. Signal delayed into the other input of the XOR.
 
Your right...
I will use NANDS to do the XOR (see image) being my output B' my input B. My output B' it's after my RC network.
Thanks to all...
Merry Christmas.
 

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I think that the initial ideia (with Ron H help) with XOR won't work, because when my signal goes down 0 and 0 with XOR is 0, and i want to do a 1 level
 
What Ron is saying is you should delay one of the XOR inputs. The time delay on the second input will have direct control over the pulse widths on the output, so in this example, you will need to the know the output delay times of the two inverters (tPHL and tPLH). Before anybody whines, there are other ways to generate a delay as well.
 

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You don't need 2 ICs. Use unused sections of the XOR as the delay.

If you connect a High to one input of an XOR, it acts as a non inverting buffer.

Alternatively, if you connect a Low to one input of an XOR, it acts as an inverting buffer.
 
ljcox said:
You don't need 2 ICs. Use unused sections of the XOR as the delay.

If you connect a High to one input of an XOR, it acts as a non inverting buffer.

Alternatively, if you connect a Low to one input of an XOR, it acts as an inverting buffer.
and the pulse width would depend on the input-to-output response time of the gates. won't it be too fast/ too narrow pulse
 
You can call it nitpicking if you wish, but the point I was trying to make is that an XOR can be used as either an invering or non inverting buffer.

Beginers may not know that.
 
This threads getting quite long now, and producing a little controversy, but it's never been explained what it's required for? - with full information a solution may be much easier?.
 
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