ca65 V2.13.3 - (C) Copyright 1998-2012 Ullrich von Bassewitz
Main file : monitor_test.s
Current file: monitor_test.s
000000r 1
000000r 1 .debuginfo +
000000r 1
000000r 1 .setcpu "65C02"
000000r 1 .macpack longbranch
000000r 1
000000r 1 ;
000000r 1 ; constants
000000r 1 ;
000000r 1 STACK := $FC
000000r 1 ;
000000r 1 ; define PICIO page in memory map and UART registers
000000r 1 ;
000000r 1 PICIO := $DF00 ;
000000r 1 PIR1 := PICIO + $9E ; TX1IF & RC1IF flags
000000r 1 TXREG1 := PICIO + $AD ; uart TX register
000000r 1 RCREG1 := PICIO + $AE ; uart RX register
000000r 1
000000r 1 .segment "MONITOR"
000000r 1 .org $FF00
00FF00 1
00FF00 1 ;***********************************************************
00FF00 1 ; Reset *
00FF00 1 ;***********************************************************
00FF00 1
00FF00 1 Reset:
00FF00 1 A2 FC LDX #STACK ;
00FF02 1 9A TXS ;
00FF03 1 ;
00FF03 1 ; Display startup message
00FF03 1 ;
00FF03 1 A0 00 LDY #0 ;
00FF05 1 StartMsg:
00FF05 1 B9 35 FF LDA Msg,Y ;
00FF08 1 F0 06 BEQ Loop ;
00FF0A 1 20 1A FF JSR Put232 ;
00FF0D 1 C8 INY ;
00FF0E 1 80 F5 BRA StartMsg ;
00FF10 1 ;
00FF10 1 ; Echo characters from terminal
00FF10 1 ;
00FF10 1 Loop:
00FF10 1 20 27 FF JSR Get232 ;
00FF13 1 90 FB BCC Loop ;
00FF15 1 20 1A FF JSR Put232 ;
00FF18 1 80 F6 BRA Loop ;
00FF1A 1
00FF1A 1 ;***********************************************************
00FF1A 1 ; Put232(ACC) subroutine *
00FF1A 1 ;***********************************************************
00FF1A 1
00FF1A 1 Put232:
00FF1A 1 48 PHA ;
00FF1B 1 Txwait:
00FF1B 1 AD 9E DF LDA PIR1 ; RC1IF & TX1IF flag bits
00FF1E 1 29 10 AND #%00010000 ; TX1IF = 1 (tx ready)?
00FF20 1 F0 F9 BEQ Txwait ; no, branch (wait), else
00FF22 1 68 PLA ;
00FF23 1 8D AD DF STA TXREG1 ; send character
00FF26 1 60 RTS ;
00FF27 1
00FF27 1 ;***********************************************************
00FF27 1 ; Get232() subroutine returns character in ACC *
00FF27 1 ;***********************************************************
00FF27 1
00FF27 1 Get232:
00FF27 1 AD 9E DF LDA PIR1 ; RC1IF & TX1IF flag bits
00FF2A 1 29 20 AND #%00100000 ; RC1IF = 1 (rx ready)?
00FF2C 1 F0 05 BEQ NotRx ; no, branch (exit), else
00FF2E 1 AD AE DF LDA RCREG1 ; collect Rx char
00FF31 1 38 SEC ; indicate data available
00FF32 1 60 RTS ;
00FF33 1 NotRx:
00FF33 1 18 CLC ; indicate data not avail
00FF34 1 60 RTS ;
00FF35 1
00FF35 1 Msg:
00FF35 1 0D 0A 4B 38 .byte $0D,$0A,"K8LH raw test",$0D,$0A,$00
00FF39 1 4C 48 20 72
00FF3D 1 61 77 20 74
00FF47 1
00FF47 1 ;***********************************************************
00FF47 1 ; 65C02 Vectors *
00FF47 1 ;***********************************************************
00FF47 1
00FF47 1 .segment "VECTS"
00FF47 1 .org $FFFA
00FFFA 1 00 FF .word Reset ; NMI
00FFFC 1 00 FF .word Reset ; RESET
00FFFE 1 00 FF .word Reset ; IRQ
010000 1
010000 1