I make crystal oscillators for a living.
The duty cycle on logic output oscillators is normally quoted at the midpoint between the high and low output voltages. For CMOS output oscillators that is almost always at half the supply voltage. Also most oscillators are designed to have a 50% duty cycle, but there will be a tolerance on that.
Oscillators below about 10 MHz are usually made by dividing the crystal frequency so the duty cycle will be very near to 50%. As you get to higher frequencies, there is no divider so asymmetries in the section that actually oscillates will be passed directly onto the output.
Also at high frequencies, the rise and fall times take a significant fraction of the cycle time, so if the rise and fall times differ, that will vary the duty cycle.
That is why the duty cycle is not exactly 50%, and is usually quoted as 45 to 55%. For most oscillator users it isn't important so that is why the specification isn't tighter at lower frequencies, where in practice the duty cycle will be closer to 50%.