Dear colleagues,
At the moment I work on designing a device and I can't understand which principle/rules should be used to select a DC/DC and LDO for power supplying digital ICs. I have the following ICs - 6 sensor with I2C bus, GNSS on a separate pcb, ARM STM32, display control, display backlight, LAN. All ICs are powered from 3.3 volts. The two additinal sensors are powered by 5 volts. The device will be powered from general external AC/DC 120-220/5V, backup power from 12 volts.
My vision is the following: 12 volts step down to 5 volts using a low-noise DC-DC. Then 5 volts step down to 3.3 volts using a low-noise LDO. I need to power 11 chips so that there is minimal impact on all 11 chips between each other and I would like to pass EMC/EMI Testing and Certification. Also, I don't understand if I need to use a Ripple Blocker LDO for each IC? When laying out a PCB, how often should ground layers be used? Device will not be produced in the millions and I would not like to save on the components.
I would be thankful if you would help me with your advice and recommendations.
Best wishes
Georg