resistor causes slow rise time?

[alphadog]

I read that if you want to level shift 5V to 3.3V, using a resistive divider, than the added resistors will slow the rise time of the signal.

Why is that?

The 3.3V output voltage of the resistive divider has no time delay relative to the 5V input voltage.
V_out(t) = R1 / (R1 + R2) * V_in(t), where is the time delay here?

 

[crutschow]

The increase in rise-time results from the RC time constant due to the divider equivalent output resistance and the stay capacitance on the divider output due to trace/wire capacitance and the input capacitance of the IC being driven by the signal. This stray capacitance is typically in the tens of picofarads, depending upon the length of the traces/wires and the number of inputs being driven.

 

[alphadog]

Thanks, i havent though about it.
In this article they offered to use a buffer,
How would that solve the problem of the stray capacitance and rise time?

 

[dknguyen]

THe buffer just adds more current capability to overcome the resistance in order to charge up the capacitance faster, thus reducing the rise time.

It would be like a mechanical engineer who has a plane that is too heavy to fly. Sticking a bigger engine into it would be like using a buffer. Whereas reducing the weight of the plane would be more like reducing the resistance and stray capacitance.

 

[alphadog]

Thanks!

So you say the buffer decrease has lower resistance then the resistance in the resistive divider circuit, and therefore the capacitor charges faster?

 

[Willbe]

You're supposed to use a compensated divider network, each resistor being shunted by a small capacitor.

 

[alphadog]

What do you mean in saying "each resistor being shunted by a smaill capacitor"?

 

[Roff]

There's a good chance that the delay will be insignificant in your application. Where does your level-shifted input come from, and where does the output go? Part numbers of devices would be helpful, and the clock rate, pulse width, or whatever speed-related info you have.

 

[mneary]

What do you mean in saying "each resistor being shunted by a smaill capacitor"?

If you know what the stray capacitance in the 3.3V traces are, it is possible to put a capacitor in parallel with the 'upper' resistor in the divider which creates a capacitive voltage divider at the highest frequencies.

As Roff said, this is a measure you only take with high speeds. Your current projects are unlikely to need this level of attention.

 

[Willbe]

What do you mean in saying "each resistor being shunted by a smaill capacitor"?

I could only find this link-
Voltage divider - Wikipedia, the free encyclopedia
In effect you put a capacitive divider in parallel with a resistive divider so that the division ratio is the same at DC as it is at high frequency AC.
Compensated o'scope probes use this principle.