I read that if you want to level shift 5V to 3.3V, using a resistive divider, than the added resistors will slow the rise time of the signal.
Why is that?
The 3.3V output voltage of the resistive divider has no time delay relative to the 5V input voltage.
V_out(t) = R1 / (R1 + R2) * V_in(t), where is the time delay here?
Why is that?
The 3.3V output voltage of the resistive divider has no time delay relative to the 5V input voltage.
V_out(t) = R1 / (R1 + R2) * V_in(t), where is the time delay here?