return current traces.

Hey everybody,

I'm using MCU which communicates with Flash memory by SPI protocol.
I'm asking you how should I trace the DGND in each IC, so SPI lines with high frequency wont create large loops and therefore will become quite large inductors with high impedance.

Thanks

electricity86 said:

Hey everybody,

I'm using MCU which communicates with Flash memory by SPI protocol.
I'm asking you how should I trace the DGND in each IC, so SPI lines with high frequency wont create large loops and therefore will become quite large inductors with high impedance.

Thanks

Click to expand...

The rule of thumb for return currents is that at low frequencies the return current follows the path of least resistance, but at high frequencies it fllows the path of least inductance. What that means is at high frequencies the current will try to minimise the 'loop area' created by the signal and the return path. To minimise the loop area you should route the signals so that they have a DGND trace under or adjacent to the signal throughout the length of the signal.

Normally this is done using a ground plane under the signals. Multi-layer PCBs are the way to go with a ground plane under the signals for best results.

A good reference for this is "High Speed Digital Design: A Handbook of Black Magic" by Johnson and Graham, see here. This is an excellent book, jammed with useful stuff, highly recommended.

Mark.

Thanks perky!
You helped me alot!

electricity86 said:

Thanks perky!
You helped me alot!

Click to expand...

You're welcome