Schematics where SR-flipflop is drawed with one output inverted

Hi.

I assume tha picture uses just regular SR-ff, but why bother drawing inveted output symbols at it?

Further on - why draw the inverted output at oposite outputs on those two SR-ff?

Personally I never draw any invert symbols onto SR-ff on schematics, as it just leads to more confusion

That schematic uses a whole bunch of unconventional symbols [&] for an AND gate. The gates are rectangular, etc. Note that, in general, there is no Q and ~Q labels, so the inversion accomplishes that. So, in this application, probably the templates were not available for the gates.

As for "further on"; Probably to make the schematic more readable without crossing wires.

KeepItSimpleStupid said:

That schematic uses a whole bunch of unconventional symbols [&] for an AND gate.

Click to expand...

Nothing wrong with that. It's european standard.

But - talking of unconventional symbols, the SR-ff sure is.