The device appears to be SPI compatible, with data to D0 and clock to WR, with the data load on the positive edge or WR.
You need to send four bits per device output, so 16 bits for the four output device.
Pulse LAT low after transferring all data, to load the control registers from the SPI input shift register.
The only restrictions I can see are minimum times for date setup and hold, and the delay from the final WR before the /LAT pulse.
The maximum SPI speed looks to be around 3MHz and with minimum 80nS delay from last WR to /LAT. Slower clock and longer delays are fine.
(The clock rate could be higher with different data/clock timing, but for simple SPI with the clock edge in the middle of the data, 3MHz is a safe limit).