SDRAM issue

[spectrum]

Dear all,

i have a strange issue in a little board i developed, i am trying to debug it, but is the first time i am developing a circuit with sdram, and i can't get out alone, maybe here someone with sdram experience could help me with some checks/hints:

I have a MCF5307, connnected with an SDRAM from Micron, type MT48LC4M32B2 (16Mbytes).

Clock for the cpu is generated from an external oscillator, 40 Mhz. CPU speed is 2X (80Mhz, through PLL), but BUS_CLOCK exit from the CPU and that go to the sdram is divided by 2, so 40 Mhz.

The issue is the following: i run a simple strartup SDRAM test program, directly from inside de Micro SRAM: i write and read back, dword by dword, values to the external SDRAM, stepping through all the 16MB.

For an undefined period of time, can be of 10 minutes or hours, the test succeed. Then, suddenly, the test start fo fail at random locations (value read back is different from the value just writtten).

What could "probably" be excluded:
1) power supply, is 3.3 and seems quite stable, low ripple, low noise.
2) solderings, i checked many and many times, had this same issue also in another board.
3) SDRAM init sequence, is copied from other working applications.

What i think can be source of issues:
1) Clock, maybe is not stable, or have some drift in itime.
2) wiring issues, bus clock is 40Mhz, i don't know some non perfect ADDRESS/COLUMN/ROW signal wiring can cause the issue.
...

Any kind of suggestion is really appreciated.
Many thanks
Angelo

 

[blueroomelectronics]

Post your schematic.

 

[spectrum]

sorry for the delay, i was travelling for job and could upload the diagram now only.

Let me know if something else is needed.

In the meantime i did some tests:
1) well-cleaning of bus and SDRAM control signals using acetone, to avoid that some flux part create some problem at 40Mhz.
Nothing is changed.

2) reduced the bus clock at minimum, using the divider settings, from 40 to 20 Mhz.
Still memory test fail.

Strange thing: sometime happen that i refresh the soldering of some pin of the sdram memory chip, and just after (chip pins someway still hot) the memory test pass for all the 16M for some monites.

thanks,
Angelo

 

[mneary]

It looks very much like your series resistors (R5, RN4, RN5) for DRAMW, SCKE, RAS and CAS have the same signal names on both ends, meaning that they aren't actually contributing to signal quality.

 

[Mikebits]

It looks very much like your series resistors (R5, RN4, RN5) for DRAMW, SCKE, RAS and CAS have the same signal names on both ends, meaning that they aren't actually contributing to signal quality.

Good eye mneary, I guess DRC would not catch that, shorted resistors might even degrade signal quality.

 

[Mikebits]

I guess my first approach would be to grab a digital scope and start checking signal quality on the control and clock lines, and after that grab a logic analyzer to check timing.

 

[mneary]

Good eye mneary, I guess DRC would not catch that, shorted resistors might even degrade signal quality.

Shorted resistors are an indication that nobody has inspected the route of the critical traces. Bad omen.

 

[spectrum]

hi all,

thanks for the reply.

No, signal names are not the same, one end have a "_" symbol, there are no shortcuts.
Since this is my first prototype with SDRAM, certainly the wiring can be quite bad.
I prepared a spectra (.dsn) export of the PCB

**broken link removed**

PCB has been done with kicad, i hope you can look at it, for example using FreeRouting : home

thanks again,
Angelo