Searching for Synchronous Buck converter NFETs?

Flyback said:

As you know, a NFET for a Sync Buck must have Cgd at least 100 times less than Cgs.

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No, I don´t know that, never head about such criteria ever. Where did you get that from?

here they say the ratio should be less than one, not hundred, page 28: https://www.ti.com/lit/ds/symlink/t...46891&ref_url=https%3A%2F%2Fwww.google.com%2F

Its so you dont get spurious on-turning when the opposite fets turns on...there are many app notes on it on the www.
ti.com even used to make a synch buck fet pair to counter the issue.
Its Qgd/Qgs <1 and Cgd/Cgs <1/100

Flyback said:

Its so you dont get spurious on-turning when the opposite fets turns on...

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I thought the way you do that is to allow for deadtime in the switching waveforms and put a Schottky in parallel with the body diode for the "OFF" FET.

As far as finding a device you need to develop relationships with FAEs that work for manufacturers and distributors. Please tell me you have established those contacts.

It seems like datasheets from IR don't have explicit values for those parameters but rather one or more graphs that show a variation of related quantities, Ciss, Coss, and Crss with respect to Vds.

Thanks, so anyway, for Sync Buck Bottom FET, Cgd must be << Cgs. But as we know, if the d(Vgd/dt) is high then Cgd appears to be higher since Cgd(apparent) = i.(d(Vgd)/dt). So yes, its not just Cgd that we must look at...but Qgd. And we must review Qgd at the actual Vin. The higher that the Buck's Vin is...the lower must be the ratio of Cgd/Cgs.
In the attached sim we see how the ringed capacitor being lower reduces the spurious turn-on of the low side FET.

And of course, tying in with the top post......Logic level FETs are much more susceptible to this spurious turn-on, simply because their Vgs(th) is so much lower. And when logic level FETs are used in Synch Bucks with Vin's > 30v, then things just get worse and worse.

Basically if you are doing a Synch Buck with Vin > 30V, then you really want to be throwing logic level FETs into the Bin. They are way to
susceptible to spurious turn ON when the top side FET turns ON.

Also, its noteable that Qgd/Qgs must be <1, though during spurious turn on in sync bucks, the lower FET actually has its gate shorted to ground by the driver, (and via any series resistance which would be low value)....so in fact, it makes you wonder why "Qgd/Qgs < 1" really applies in real life?

For that level of power, you will probably need a dual phase solution. Look at the LTC3890, not the LTC3891. The low side FET needs to have low RDSON only, not low QG. The high side FET needs to have a good balance between low QG and low RDSON. These 2 characteristics are normally mutually exclusive, so a low RDSON FET will have a high QG. Look for a FET with a good Figure of Merit (FOM) for the high side FET as this represents a good trade off between QG and RDSON.

For the low side FET, a low RDSON means a high QG and this high input capacitance (which is similar to QG) will help to reduce the feedthrough that comes back at the Gate drive (via the Miller capacitance) when the switch node flies positive.

A parallel Shottkey diode across the will help reduce the current injection into the body diode that happens during the dead time between the FETs switching.

So... go onto Vishay's website and download all NFETs. Delete the ones that are too low in voltage and current. Construct a column called FOM which is QG * RDSON. Sort the FOM column and pick the FET with the lowest FOM. This is your high side FET.

Then sort the NFETs by RDSON. Pick the one with the lowest RDSON. This is your low side FET

The ideal package is one with no leads, so the PowerPAK SO8 is a good one.

Simulate. If the FETs heat up too much, move from the 3891 to the 3890 and design a dual phase solution.

A parallel Shottkey diode across the will help reduce the current injection into the body diode that happens during the dead time between the FETs switching.

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Thanks, i was thinking of doing this as you say, to reduce reverse recovery current....will seek an SMB package Schottky that can handle the 16A or so of current that it must handle for the albeit short interval of time.
-I even suspect that this, may actually help reduce the spurious turn on effect.

I must admit cost is a big guiding factor for us...at the moment i have CSD18533Q5A for top fet and CSD18563Q5A for bottom fet. CSD18563Q5A has Qgs>Qgd
Thanks yes we will do dual....

The parallel Shottky will add about 3% efficiency