Signal hole detector

[glorimda]

I'm designing a circuit doing role of detecting signal drop from the microphone. This is purposed to do some range test of product. By receiving the signal through the microphone, while receiving the signal, outputs 5V, otherwise outputs 0V.
I'll put the 1Khz sine wave to microphone, amplify the signal and make it to square wave at comparator. Then through peak detector, it keeps that output fixed at 5V while there's signal, and if signal is dropped more than certain period, it goes to 0V.( This period is determined my adjusting the value of peak detector components and current circuit has around 250ms).
In the simulation program, I can get the right and intended result. But in real, sometimes it works well sometimes not. When I stop putting the signal, it sometimes still stays at 5V. So I looked into each part and I figured out that when the output is 5V even without signal, there is voltage rise at R11. So postive input of comparator(U3) is getting higher than negative input and it outputs 5V. But when it works right(no signal and 0v output), there is for sure voltage drop at R11.
I can't seem to find any reason myself and 'm stuck in here for a while.
Can anybody give me any idea or help about that?

P.S. pulse(v3) and Switch(S1) is to give some signal off time. So you don't need to care about it.

 

[ericgibbs]

hi,
Its possible that C6 is becoming charged slightly positive due to the output of the comparator being at +5V , causing the comparator to latch.

As a quick check remove C6.

 

[glorimda]

I though about that as well, but if that is the reason, the output should be 0 eventually. But it stays at 5v forever once it's going wrong. But anyway I'll check it out with getting rid of it tomm and will post it. cuz I don't have it right now here.

 

[ericgibbs]

I though about that as well, but if that is the reason, the output should be 0 eventually. But it stays at 5v forever once it's going wrong. But anyway I'll check it out with getting rid of it tomm and will post it. cuz I don't have it right now here.

hi,
The hysteresis voltage on the comp input due to the output of the comp being high will hold the comp 'latched' on.
Under certain conditions C6 would become slightly positive.

 

[Roff]

To expand on Eric's last post:
When your input signal goes away, the voltage at the output of U1 goes to VBIAS. Schmitt trigger (U3) will stay in whatever state it was in when U1 went to VBIAS.
In your sim, the mic signal (apparently) always goes away when the Schmitt output is low, so it will stay in that state. In the real world, the mic signal may go away when the Schmitt output is high OR low, and it will stay in that state.
This is because your Schmitt thresholds are symmetrical around VBIAS.

 

[glorimda]

Sorry for late bring the result back. have been pretty busy to find way of that problem. ericgibbs // as you said, I could get it solved by removing C6. Thanks for that, but unfortunately my colleague told me that it's not the fundamental cause and I need to find that. And I need c6 placed there for low-pass filter as well. As Roff said, I figured out that when the signal goes off with 5V of output at the comparator, the output pull the positive input high and even if there's no signal, positive gets higher than negative and this was the reason. So I put another voltage divider from Bias Voltage(U2) to negative input higher than positive when signal goes off. So I've solved this basically, got another problem though.
BTW,when I use comparator, do I have to always care about this situation? (status of output)
Thanks to both and attaching the modified circuit picture.

 

[ericgibbs]

hi G.
You have not said what the 'other' problem is.??

I guess you already known that positive hysteresis shifts the threshold switching point of the comparator.
If the shifted voltage level is greater than the Vref of the divider voltage the comparator will remain latched in the High output state.

In your earlier tests, depending when you blocked the microphone test signal, ie: high or low peak of the test sine the comparator would sometimes remain latched high, as you have found.
If you can somehow sync the zero crossing point of the test sine with the test blocking signal, that should give the required signal at the comparator input.