Note: Revised #'s with non-toasted FET.
Ok I went back and did some testing now that I understand the difference between source and drain loads. What I tested was with no load at all, just an open drain and a voltmeter to measure the potential between the +12v and +5v rails and the drain.
I tried driving the gate at two different voltage levels, from both a +5v and +12v source with a 1k gate resistor. Connecting either directly to gate resulted in the solder melting off the leads.
I tried testing with an 87 ohm resistor but it burned my finger :-/ In the end I used a 1k gate resistor to limit the current.
There figures are all with source connected directly to ground.
Voltages were:
Actual +5v voltage level: 4.99v
Actual +12v voltage level: 13.78v
+5v to gate through 1k resistor:
Voltage at gate: 4.98v
Voltmeter w/red lead connected to +12v rail, black to Drain: 13.78v
Voltmeter w/red lead connected to +5v rail, black to Drain: 4.98v
+12v to gate through 1k resistor:
Voltage at gate: 13.78v
Voltmeter w/red lead connected to +12v rail, black to Drain: 13.78v
Voltmeter w/red lead connected to +5v rail, black to Drain: 4.99v
This FET, STD16NF06L, is supposed to have a Vgs threshold of 1v minimum, no typ or max rated.