Try this:
The 555 represents the VCO, whatever that turns out to be.
The switch is the gear pedal(?) trigger.
Unused inputs should be grounded on the 4013s.
In the idle state, all three Ds are reset, so the /Q from the third is high.
Triggering the switch clocks that in to the first D, setting the Q output.
When the next edge from the VCO occurs, the second D is set high - and the output connection to the right.
The second positive VCO edge clocks the high state into the third D, which resets the first two. The third D is then itself reset by the next VCO edge.
It's self-debouncing, as long as any switch bounce duration is less than two VCO cycles at the highest frequency.
[Diagram drawn using this site:
https://www.circuit-diagram.org/editor/ ]
Edit - looking back, it's almost what Analogkid suggested - but the second D must also be reset by the third, and they must be synchronous registers; SR could not work, in any way I can think of at least.
I think an appropriate shift register IC that has a synchronous reset could work in place of two, two section ICs.