Hello
Some time ago I had similar question for one of my projects.
I explained it to myself this way:
View attachment 146492
Seuuence:
1)Pulse rising edge
AC current can pass through capacitors. So when +12V rising edge of HIGH pulse arrives to left side of the capacitor, it's right side also became +12V at the same time.
Or one can say capacitor allows deltaV = +12V to pass from left to right side.
2)Pulse HIGH plato
Right after rising edge, there is HIGH plato of the pulse at left side of the capacitor. But HIGH plato is DC, and capacitors block DC, so there is no current flows through the capacitor during this time, and right side of the capacitor does't charging more.
Or one can say capacitor does not allow Vplato = +12V to pass from left to right side.
But the same time right side of the capacitor (charged during rising edge) begin to discharge through load resistance, and have enough time to drop, say, to +2V.
3)Pulse falling edge
Left side of the capacitor drops from HIGH +12V to LOW 0V, so change in voltage on left side is -12V;
But capacitor tries to keep voltage across itself as before (Capacitor opposes to voltage changes, inductor opposes to current changes),
so right side of the capacitor also undergo -12V change. So right side of the capacitor is 2V-12V = -10V now!
Or one can say capacitor allows deltaV = -12V to pass from left to right side.
This process is duty cycle and frequency dependent and load dependent because right side of the capacitor must have enough time to discharge, so when falling deltaV = -12V pases from left to right side, voltage on right side already low enough to become negative