Switching factor in Cmos

Hi there,
The dynamic power dissipation of Cmos is given by
P=a*C*Vdd(square)*f
where a is the switching factor which is the probability of output switching from 0 to 1. Can somebody provide more details on it? I would appreciate if you could explain with an example?

I'm no expert on semiconductor theory but I'd be very surprised if 'a' has anything to do with probability. I would expect it, however, to be a function of the CMOS fabrication parameters, e.g. feature size and doping levels. Any experts out there?

Edit: On second thoughts I suppose the period for which a gate switching state is in the twilight zone between 0 and 1 is probability related, and that probability is dependent on doping levels etc.

The only characteristics of the semiconductor process that affect the switching power dissipation are those that determine the capacitance at the node. It's the charging and discharging of this node that causes the dynamic power loss.

"a" does appear to be the switching probability, that is the percentage of the clock frequency for that particular node to be switching from 0 to 1. This will depend upon the characteristics of the circuit driving the node. For example the nodes of a N-bit counter will each switch at 1/2 the frequency of the previous stage with the final stage switching a 1/(2^N) of the input clock frequency. Each stage will thus dissipate 1/2 the dynamic power of the previous stage.

For example the nodes of a N-bit counter will each switch at 1/2 the frequency of the previous stage with the final stage switching a 1/(2^N) of the input clock frequency. Each stage will thus dissipate 1/2 the dynamic power of the previous stage.

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Agreed. But isn't that taken care of by the 'f' factor rather than the 'a' factor, since 'f' halves with each succeeding stage?

alec_t said:

Agreed. But isn't that taken care of by the 'f' factor rather than the 'a' factor, since 'f' halves with each succeeding stage?

Click to expand...

In my example, "f" was the clock frequency.