Sync Buck FET driver with too low dead time? (LTC4449)

[Flyback]

Hello
This sync Buck FET driver has extremely low dead time of 13ns between top fet driven off and bottom fet being driven on (and vice versa) . This is far too low. Do you know why it is so low?

The simulator (LTspice) shows it giving serious shoot-thru current spikes of 100 Amps plus.

LTC4449 (sync Buck FET driver)
http://cds.linear.com/docs/en/datasheet/4449fa.pdf

 

[ronsimpson]

Did you get a job?

I don't think this is shoot through.
Left side, green trace is bottom gate drive, G-S of bottom FET 192.12uS
Blue trace is top gate G-S of tip FET 192.19uS.
Red is current in M1 FET. 56A I noticed that the M1 has about the same current spike that looks like shoot through.
I think the current in M1 is negative 2.3A when M2 turns on. So the current has been going through the body diode. You can see the D-S voltage of M1 is -0.7 volts at this time between when M1 is turned off and when M2 is turned on. I think you are fighting a slow RR time in the diode.

There is a two fast diode fix for this.

 

[Flyback]

Yes thanks, back in the world of electronics work.
Youre right, i forgot to put in the parallel schottkys....anyway.....i still dont like this 13ns of dead time, its far too low, and i will seek a ti.com sync buck driver or other, as 13ns is just way too low.
As you know, even with pllel schottky i will still get some rev rec of the intrinsic fet diode.

 

[Flyback]

with a fet with quicker internal diode, but with a bigger gate drive series resistor, there is definetely shoot through....as this ltspice shows. It shows the ltc4449 isnt doing the datasheet thing of checking ones off before it turns the other on

 

[simonbramble]

This is not shoot through. With shoot through you don't get the -700mV steps at the switch node because the low side FET (which is On when it shouldn't be) clamps the switch node at 0V. Your circuit has negative steps these implying that the bottom FET body diode is conducting when the top FET switches ON. As Ron says, you are switching on the high side FET into a conducting low side body diode and this current spike is the reverse recovery of that body diode

 

[Flyback]

sorry but in post #4, its definetely shoot thru........the ltspice sim attached here prooves it, because the LHS has turn-off diodes which solves the shoot thru problem....reverse recovery happens in both RHS buck and LHS buck.
Anyway, the rhetorical question is, -does this happen with the LTC4449 in real life.

And theres no way we are going to risk a chip which states just 13ns of dead time......if linear.com dont do something with longer dead time, then please excuse our chicken nature, but we will pick some other manufac for this part. 13ns is just too "knife edge" for comfort.

 

[alec_t]

Looks like shoot-through to me (which would coincide with diode recovery). If you plot the Vgs voltages of M3 and M4 there's an overlap point where they are both about 2.3V, their turn-on threshold, even though the TG and BG outputs of the 4449 don't overlap.

 

[ronsimpson]

Looks like shoot-through to me

I am looking at M1, M2 (right side) At 699.83uS
I think M1 voltage rise time is so fast that the 10 ohms gate resistor can not keep M1 turned off.
Look at the out put of U2-BG and the M1 gate voltage. The voltage on U2-BG drops fine but during the rise time the gate voltage rises back up and turns on M1.

To slow down the rise time by added capacitance which helps. Capacitance from M1-D/M2-S to ground.
AND
I reduced the 10 ohm gate resistors to 2 ohms helps. Then to double prove I change to 100 ohms which leaves M1 on for a very long time.

Bottom line, I think the capacitance in the MOSFET is so high that 10 ohms causes problems. Try changing to 20 ohms or 50 ohms and watch the current spike to up.

 

[alec_t]

The voltage on U2-BG drops fine but during the rise time the gate voltage rises back up and turns on M1.

The 4449 datasheet makes that very point. The drain-to-gate capacitance of the bottom FET causes its gate voltage to rise to the turn-on threshold when the top FET turns on.

 

[Flyback]

Yes, the answer to preventing the bottom fet turning on when the top fet turns on is to have the bottom fet held hard off by a separate low resistance turn-off channel in the fet driver, as in the ucc27511….
https://www.ti.com/lit/ds/symlink/ucc27511.pdf
…however, despite this feature being massively useful, no synchronous buck fet drivers actually implement this.

 

[ronsimpson]

Back when I started MOSFETs were not good or available so we used transistors.
There is an art form to drive large transistors.
There was a series of base driver ICs.
..There was a out pin that set the base_on_current. Ibase might be set to 1/10 collector current.
..There was a different pin to pull the base down. During "storage delay" time we would pull down at about full collector current.
Any way the two pins (pull up and pull down) allowed for options.
--------------------edited-------------
Been thinking.
If you had a 12V driver not a 5V driver you could hold the gate at -5V while MOSFET is off. This way it would take more current to turn on the gate. The miller effect cap would get charged faster.

 

[simonbramble]

Post #4 is definitely shoot through. The original post I was looking at is NOT shoot through - because you have the negative steps on the switch node. Try putting a resistor in series with the BOOST pin of the LTC4449. This will slow down the top FET turn ON time, but not slow down the turn OFF time. Remove the series gate resistors. My simulations show this drastically reduces the drain current pulse you are worried about.

Why are you using FET drivers in the first place? Is it to get the gate-source drive voltage up? The LTC3892 has got higher gate drive voltage, so this is the chip I would use... Problem solved

 

[Flyback]

ltc3892 has higher current sense ref voltage, so we are only using ltc3892 for our Dual buck 48v to 13v3 at 13A converter......for the 24v to 1v5 at 12A converter, we are using ltc3774.....(it has lower sense ref voltage)...also, the ltc3774 looks more suitable for having 8 bucks into one output. As you know, the ltc3774 demands one uses the external gate driver...this isnt so much a bad thing though, since we beleeve it makes pcb layout of the high di/dt gate loops easier anyway.
The ltc3774 allows the 8 bucks to be totally interleave phased.

 

[ronsimpson]

I took the gate resistors form 10 to 2.2 and that helped. Moving them to 50 ohms made it much worse.
I also wanted to make the edges resonant so tried adding 2200pF across D10.
I have made these (at 400 volt supply) where I added a large amount of capacitance. The FETs ran cold. Would not run with a light load but did not have to.
D10 has no current so can be removed.