Hi,
My knowledge of delta modulation is hazy at best. Generally, what ever your modulation scheme, synchronisation is usually performed with a PLL. If I understand the methods correctly, delta modulation is 'similar' to PWM (not quite though), its just a stream of 1's and 0's. So at the begining of a packet/frame, a string of alternating 1's and 0's would yeild a square wave of fixed frequency/phase. When demodulated, that should give a flat signal.
Lock onto that with a PLL (recommend a DPLL for large bandwidth, and accuracy)and it will be the reference clock for the Rx. That would give you the 'bit-rate' so you should be able to generate a sampling clock from it, and therefore, demodulate it. A PLL, if tuned to your bit-rate' probably wouldn't need a syncronisation pattern at all, it would happily pluck the highest frequency from your stream. As long as your Rx knows the datarate of the Tx.
There are alternate methods to a PLL. Some simple logic works wonders with syncronisation, counters, and edge-detectors.
I hope thats what you're after, I'm no expert, can barely remember anything from uni.
Blueteeth