I want to simulate the attached circuit but the following error occurs:
(the wheatstone bridge is unplugged and I don't use it)
Where do I change in the settings the timestep?
I searched but I don't know where it is. I went to the simulation control panel and there are so many parameters: Gmin, Abstol, Reltol etc. does anyone know how to fix it?
I tried putting ESR to each capacitor, but same error.
Help message for "time step too small" (include quotes)
"The simulator cannot find a short enough time step to make the current nonsingular, and a "time step too small convergence fail" message is issued."
Choose a realistic Rser to limit startup current to avoid a singularity that demands a 0 time step. (too small)
If load regulation error is 1% on 12V @ 1A then Rs= 0.12
Messaggio di aiuto per "passo temporale troppo piccolo" (includere virgolette)
"Il simulatore non riesce a trovare un passo temporale sufficientemente breve per rendere l'attuale non singolare e viene emesso un messaggio "passo temporale troppo piccolo convergenza fallita".
Scegliere un Rser realistico per limitare la corrente di avvio per evitare una singolarità che richiede un passo temporale 0. (troppo piccolo)
Se l'errore di regolazione del carico è dell'1% su 12V @ 1A allora Rs= 0.12
Thanks for the answer! I don't understand where I have to place Rser ... is it the resistor in series to the input generator? Or in series in the opamp power supply?
If you mean a resistor in series at the power supply of the opamp (+12V) ... I tried but the error remains
I want to simulate the attached circuit but the following error occurs:
(the wheatstone bridge is unplugged and I don't use it)
Where do I change in the settings the timestep?
I searched but I don't know where it is. I went to the simulation control panel and there are so many parameters: Gmin, Abstol, Reltol etc. does anyone know how to fix it?
I tried putting ESR to each capacitor, but same error.
The models you are using aren't very good and struggle to converge. Use the UniversalOpamp3b model instead. Be aware that the opamp i/o signals shouldn't be closer than 1.5v of the supply rails or they will clip/distort.
Also, in a real circuit, for the opamps, you will need to either, use split power supplies, or bias the inputs at VCC/2 to couple an AC input signal. Also need DC blocking caps at the input and output.
sometimes switching to Alternate mode helps. Go into Simulate -> Control Panel, SPICE tab and change the Engine Solver from Normal to Alternate
If you want to design a filter, please see my website. That will talk you through the design of a multi pole Sallen Key filter. It uses the LTC6240 which has an accurate model and will not give any faults. Timestep too small errors are sometimes caused by incorrect op amp models
I'm not sure if you fixed your schematic yet but a single supply needs to be biased to V+/2 at U1-Vin+ using R33. Possibly OK but ensure correct power pins for polarity.