Traces under TQFP PICs

[jimmythefool]

Hi alll,

I'm routing a board based around a 18F46K22. Very pleased with the result, except I cant route one of the vdd pins (4 total) . The only way is a very long trace, or linking across from the other side of the PIC. I checked the datasheet, but couldn't find any info on whether the PIC has a metal plate under it, and if so, is it connected to 0v.

Would it be a problem to leave that vdd pin disconnected?

 

[carmusic]

ive never seen pic that haves under metal plates, only chips that needs a lot of heat transfer has them

 

[DirtyLude]

Generally only specialized power IC's will have a thermal pad underneath when in a QFP. LED drivers, battery chargers.... When they do, they will be very clear about the proper footprint in the datasheet.

 

[dknguyen]

Just check the pinout and packaging information (it will be very obvious). And, if you have a solder mask it doesnt even matter.

Multiple Vdd pins (and muiltuple Vss pins) tend to be internally connected. You might be able to get away with not connecting it, but it limits the total current the chip can pass and limits the frequency performance by increasing power trace impedance, particularily to the local area on the die where each power or ground pin actually connects to the die- internally connected doesnt mean they all connecet to each other first and then connect to the die at the same single point. In a good design, they all connect to different points spread across the die so that no one area of the silicon die is too far away from its power or ground trace in order to minimize power/ground impedance.

And of course, it also limits decoupling, particularily to the area of the chip the unconnected pin is responsible for.

Low speed, low curent chips you can get away with it. High speed, high current chips might not work properly if at all.

 

[jimmythefool]

Thank you for your replies.
I checked the DS, and there is no metal pad under the PIC.
What I would like to do, is have a Vdd pad under the pic, with decoupling caps on all vdd pins, via'ed to the solid ground plane. I've never worked with a 64 pin TQFP before, so looking for advice

Thank you