tri-sate buffer (74126)

[vinodquilon]

I am using 74126 as tri-sate buffer to drive a D Flip Flop clock input.
That is positive edge triggering of FF is controlled by buffer.
But the problem is that when buffer is in high impedance state, output should be Logic 0.
Does there need any 100K pull-down resistors to ensure Logic 0 state ?

 

[ericgibbs]

I am using 74126 as tri-sate buffer to drive a D Flip Flop clock input.
That is positive edge triggering of FF is controlled by buffer.
But the problem is that when buffer is in high impedance state, output should be Logic 0.
Does there need any 100K pull-down resistors to ensure Logic 0 state ?

hi,
If its a 74 series F/F a 100K pull down will be too high a value, I would try a 1k.

 

[Hero999]

The power supply voltage should also be between 4.5V and 5.5V, ideally 5V.

I've heard of people confusing TTL with HC CMOS which will work from 2V to 6V.

 

[vinodquilon]

solution with AND gates

See my application linked here.

To solve all these issues I will replace 74126 with 7408 AND gate.
One input of all AND gates will be from IC9 NE555.
Other input follows from NOT gates.
Now there is no problems of high impedance states. Thus positive edge
triggering for D Flip Flops.