I am using 74126 as tri-sate buffer to drive a D Flip Flop clock input.
That is positive edge triggering of FF is controlled by buffer.
But the problem is that when buffer is in high impedance state, output should be Logic 0.
Does there need any 100K pull-down resistors to ensure Logic 0 state ?
I am using 74126 as tri-sate buffer to drive a D Flip Flop clock input.
That is positive edge triggering of FF is controlled by buffer.
But the problem is that when buffer is in high impedance state, output should be Logic 0.
Does there need any 100K pull-down resistors to ensure Logic 0 state ?
To solve all these issues I will replace 74126 with 7408 AND gate.
One input of all AND gates will be from IC9 NE555.
Other input follows from NOT gates.
Now there is no problems of high impedance states. Thus positive edge
triggering for D Flip Flops.