vinodquilon
Member
I am using 74126 as tri-sate buffer to drive a D Flip Flop clock input.
That is positive edge triggering of FF is controlled by buffer.
But the problem is that when buffer is in high impedance state, output should be Logic 0.
Does there need any 100K pull-down resistors to ensure Logic 0 state ?
That is positive edge triggering of FF is controlled by buffer.
But the problem is that when buffer is in high impedance state, output should be Logic 0.
Does there need any 100K pull-down resistors to ensure Logic 0 state ?