Thanks for the responses.
I attach a larger more readable version of the circuit. Also let me clarify a few questions & points:
1) Yes the chips are decoupled - originally they were not, and the output never latched. Once they were inserted, the output latches sometimes.
2) I appologise - i am seeing the short spike on VCC not ground. (measuring at the CLR pin)
3) The switch debounce circuit (cap+resistor) feeds a 555 with logic to generate a clean input clock pulse that aways the same length (800ms)
I have buzzed through the supply lines and checked connections, and both are 4-5 ohms to the regulator. The supply is a simple 1A +5v regulator - driven from a +12v lab supply (although i have operated this without the regulator - directly form the supply - same result)
The current draw when on (for the entire circuit - pretty big) is about 30mA
This might seem an erroneous peice of information, but i constructed the same circuit using J-K flip flops and i ALSO got a similar non-latching of the output - What on earth am i doing wrong, its driving me crazy. The only common element is the PSU - and that is a decent Lab supply. *normally* i seem to know what im doing
Thanks in advance.
Tim