Why when the signal is from -5 to +5 volt at the input if the gate is TTL i have a signal from 0 to 5volt ?
And why if it is CMOS the signal is also from -5v. to +5volt??
Thanks
i am not referring to the output signal. My problem is, in the picture, if I put a 'signal' before the resistence from -5 to +5, when i have a TTL gate, it makes that this signal at the 'input' hasen't negative component
i am not referring to the output signal. My problem is, in the picture, if I put a 'signal' before the resistence from -5 to +5, when i have a TTL gate, it makes that this signal at the 'input' hasen't negative component
TTL is a logic system, it works from 0V (OFF or LOW) to 5V (ON or HIGH), if you fed it a non-TTL signal you are likely to get unpredicable results, and you can't get anything out of it except a TTL signal.
What are you trying to do anyway, it sounds rather bizarre?.
i am not referring to the output signal. My problem is, in the picture, if I put a 'signal' before the resistence from -5 to +5, when i have a TTL gate, it makes that this signal at the 'input' hasen't negative component