rockin_rick
New Member
I am creating a general purpose (mainly robot) controller board for my personal use that includes a 'network' interface for connecting multiple copies of this board together along with anything else that I may want to connect to it in the future. I want this to be flexible for future unknown applications. I am trying to determine the reset circuit for the board (and thus network).
My design REQUIREMENTS are:
-One single hardware design
-A single master, one or more slave network arrangement
-PIC uC (most likely 16F877A, but perhaps 18Fxxxx)
-Software is customizable for each board
-Use RA4 for controlling the network reset signal since it is open collector only (in other words - save the more useful I/O for other purposes)
-Config jumpers are fine since it is for personal use, but avoid if possible for convience
-A single header pinout for the master and the slaves
-Each board have a reset button
My PERCEIVED goals are:
-Master is in charge of asserting the network reset
-Network reset is active low (/RESET)
-Slaves can enable or disable the external reset signal
-Master holds all attached devices (that choose to enable the external reset) in reset until master is ready
-The maximum number of these identical boards connected together will not exceed 3 (1 master, 2 slaves)
-Whatever 'other' unknown devices that accept an active low reset signal may be on the reset circuit (max 5-10)
-Allow devices to have different VCC's and still respond to the network reset and not effect other nodes
-Assume that slaves have pullups for their reset circuit
These are PERCEIVED goals since this is what I currently think is best, however, if someone thinks that I should do something differently, I will certainly consider changing.
Attached is my proposal of the circuit (with circuitry unessential to this topic ommited). JP1 will allow the board to be either: the master and assert the /RESET (jumper over 1-2), slave and accept the /RESET (jumper over 2-3), or neither assert or accept the network /RESET (no jumper connected). JP1 pin 2 is the network reset circuit (that is brought out to a header).
My circuit theory:
For the master: On powerup, the master's RA4 will be in a high-Z input state, and that will allow T1 to be biased on and asserting the network reset. All attached devices will be held in reset. Once the master is up and running and ready, it will change RA4 to an output and assert a low thus turning off T1 which allows attached devices to startup. Pushing S1 to reset the master will cause RA4 to go high-Z and cause T1 to turn on and hold attached devices in reset.
For slaves: S1 will reset only that individual node, not any other device on the network. An active low on the network reset line (/RESET) will reset the device and hold it in reset until it goes high.
Will this work? Should I change components or values? I suppose that D2 (5.1V zener diode) is not really necessary since D1 shouldn't allow a higher voltage to pass, huh? I suppose that I'd like to have the ability to connect nodes that have different VCC's.
Should I consider some other arrangement completely? Perhaps having each 'slave' have it's own pulldown transistor? Something else?
I appreciate any advice or critisism.
Thanks,
Rick
My design REQUIREMENTS are:
-One single hardware design
-A single master, one or more slave network arrangement
-PIC uC (most likely 16F877A, but perhaps 18Fxxxx)
-Software is customizable for each board
-Use RA4 for controlling the network reset signal since it is open collector only (in other words - save the more useful I/O for other purposes)
-Config jumpers are fine since it is for personal use, but avoid if possible for convience
-A single header pinout for the master and the slaves
-Each board have a reset button
My PERCEIVED goals are:
-Master is in charge of asserting the network reset
-Network reset is active low (/RESET)
-Slaves can enable or disable the external reset signal
-Master holds all attached devices (that choose to enable the external reset) in reset until master is ready
-The maximum number of these identical boards connected together will not exceed 3 (1 master, 2 slaves)
-Whatever 'other' unknown devices that accept an active low reset signal may be on the reset circuit (max 5-10)
-Allow devices to have different VCC's and still respond to the network reset and not effect other nodes
-Assume that slaves have pullups for their reset circuit
These are PERCEIVED goals since this is what I currently think is best, however, if someone thinks that I should do something differently, I will certainly consider changing.
Attached is my proposal of the circuit (with circuitry unessential to this topic ommited). JP1 will allow the board to be either: the master and assert the /RESET (jumper over 1-2), slave and accept the /RESET (jumper over 2-3), or neither assert or accept the network /RESET (no jumper connected). JP1 pin 2 is the network reset circuit (that is brought out to a header).
My circuit theory:
For the master: On powerup, the master's RA4 will be in a high-Z input state, and that will allow T1 to be biased on and asserting the network reset. All attached devices will be held in reset. Once the master is up and running and ready, it will change RA4 to an output and assert a low thus turning off T1 which allows attached devices to startup. Pushing S1 to reset the master will cause RA4 to go high-Z and cause T1 to turn on and hold attached devices in reset.
For slaves: S1 will reset only that individual node, not any other device on the network. An active low on the network reset line (/RESET) will reset the device and hold it in reset until it goes high.
Will this work? Should I change components or values? I suppose that D2 (5.1V zener diode) is not really necessary since D1 shouldn't allow a higher voltage to pass, huh? I suppose that I'd like to have the ability to connect nodes that have different VCC's.
Should I consider some other arrangement completely? Perhaps having each 'slave' have it's own pulldown transistor? Something else?
I appreciate any advice or critisism.
Thanks,
Rick