Using latches to capture 8086 bus

Why not externally gate /IOWR, /CS1 and /CS2, so ONLY data being written to the LCD is being latched? As it is, you are trying to read every peripheral write regardless of destination.

You then just need to check A1 and store the latched data byte as control or display data.

I'd also connect the decoded latch signal to an SR bistable, to generate an interrupt each time a new byte is latched, then reset that with an output as you read the stored data, so you can exactly track new bytes even if they are duplicates.

rjenkinsgb

Is it what you mean ?

Also which IC Latch for the following that you sugesst ? and also SR ?

The LCD is only written to when /CS1, /CS2 and /IOWR are ALL low. Looking at the signals separately is meaningless.

Connecting all three of those to a thee input OR gate (or eg. the two /CS to a two input OR, with the output of that and /IOWR to another two input) should produce a low-going pulse at each write access.

That would be OK to gate an LS373, which would capture the data at the end of the pulse when the data bus should have stabilised.

You could use eg. an LS74 with that, one half with the A1 line as its D input to capture that, and the other section with D fixed at high level as the write detect.
Both halves with the same clock as the 373.

Use the RESET input on the write detect LS74 to arm it / re-enable it after each LCD write is captured.

When a write occurs and is latched, the write detect latch will be set - use either Q or /Q to trigger an interrupt, or poll one fast enough.

Read the data from the other latches then reset that ready for the next write.

That uses a total of ten inputs and one output on the STM32.