Vectored jump

Many other CPUs have a vectored jump instruction, JMP (addr) or similar, where the destination of the jump is stored at the specified address, in counterpoint to JMP addr where the destination is the specified address itself. Is there a way of creating this functionality with the 8051 so I can have a block of routine addresses in RAM that are modifiable. Ideally, I'm wanting to construct the interupt entries to do the equivalent of LJMP (dest) instead of LJMP dest.

Thanks.

I'm not familiar with the 8051 instruction set, but a simple method on many CPUs is to just push the target address then do a return from subroutine.

That could be extended to a vector table by pushing a value stored at an index+offset.

That's the closest I've got so far. Something like:
PUSH DLO
PUSH DHI
MOV DPTR,vector
PUSH DLO
PUSH DHI
RET

similar to what I do with the Z80. It's "impure" as it requires the destination routine to start with popping DPTR back. And at 12 bytes it won't fit in the 8 bytes of space between each hardware vector entry point, $0003, $000B, $0013, etc.

Can you load DPTR with the passed value before the RET?
Why do you need to go to specific locations? Can you go to $0010, $0020 etc.

Mike.

Yes, I've been experimenting with:
MOV temp16,DPTR; save DPTR
MOV DPTR,vector
PUSH DLO
PUSH DHI
MOV DPTR,temp16 ; restore DPTR
RET

but you can't manipulate DPTR in one go, so it ends up as:
MOV temp16lo,DLO
MOV temp16hi,DHI
MOV DLO,vectorLO
MOV DHI,vectorHI
PUSH DLO
PUSH DHI
MOV DLO,temp16lo
MOV DHI,temp16hi
RET

and having to move things as single bytes, I could go to:
MOV temp8,A
MOV A,vectorLO
PUSH AREG
MOV A,vectorHI
PUSH AREG
MOV A,temp8
RET

and ensure interupts don't modify the temp location.

JMP @A+DPTR
(Opcode #073H)

Often used with a table at DPTR, and a value in A, which if the table is a series of jumps within the same page ( 2 bytes ) then you can have 128 possible jump locations... Or just CLR A, and set DPTR to the end goal location.

Regards
David.