OK thanks for pointing that out. I went over the code and made sure that even the 1-bit ports were reg for the outputs. So now that's fixed I got an avalanche of new error messages. I'm starting to get a bit desperate here. Willing to pay money for help on this.
Warning (10230): Verilog HDL assignment warning at comp4.v(126): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(127): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(128): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(129): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(130): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(131): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(132): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(133): truncated value with size 12 to match size of target (4)
Warning (10030): Net "Inst_mem.data_a[3]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.data_a[2]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.data_a[1]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.data_a[0]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.waddr_a[2]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.waddr_a[1]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.waddr_a[0]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.we_a" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Info: Elaborating entity "data_mem" for hierarchy "data_mem:data_mem1"
Warning (10235): Verilog HDL Always Construct warning at comp4.v(163): variable "Data_in" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at comp4.v(163): truncated value with size 8 to match size of target (4)
Warning (10235): Verilog HDL Always Construct warning at comp4.v(163): variable "Data_address" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(165): variable "Data_address" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at comp4.v(160): inferring latch(es) for variable "Data_out", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "Data_out[0]" at comp4.v(160)
Info (10041): Inferred latch for "Data_out[1]" at comp4.v(160)
Info (10041): Inferred latch for "Data_out[2]" at comp4.v(160)
Info (10041): Inferred latch for "Data_out[3]" at comp4.v(160)
Info: Elaborating entity "mux_3_to_1" for hierarchy "mux_3_to_1:mux_3_to_11"
Warning (10235): Verilog HDL Always Construct warning at comp4.v(187): variable "Aconst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(189): variable "Data_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(191): variable "Alu_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at comp4.v(184): inferring latch(es) for variable "Mux_out", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "Mux_out[0]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[1]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[2]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[3]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[4]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[5]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[6]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[7]" at comp4.v(184)
Info: Elaborating entity "A_mux_Accum" for hierarchy "A_mux_Accum:A_mux_Accum1"
Warning (10235): Verilog HDL Always Construct warning at comp4.v(214): variable "A_Mux" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(215): variable "x" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(217): variable "A_Mux" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(219): variable "Mux_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at comp4.v(210): inferring latch(es) for variable "x", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at comp4.v(210): inferring latch(es) for variable "y", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at comp4.v(210): inferring latch(es) for variable "A_Mux", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "A_Mux[0]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[1]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[2]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[3]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[4]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[5]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[6]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[7]" at comp4.v(210)
Info (10041): Inferred latch for "y[0]" at comp4.v(210)
Info (10041): Inferred latch for "y[1]" at comp4.v(210)
Info (10041): Inferred latch for "y[2]" at comp4.v(210)
Info (10041): Inferred latch for "y[3]" at comp4.v(210)
Info (10041): Inferred latch for "y[4]" at comp4.v(210)
Info (10041): Inferred latch for "y[5]" at comp4.v(210)
Info (10041): Inferred latch for "y[6]" at comp4.v(210)
Info (10041): Inferred latch for "y[7]" at comp4.v(210)
Info (10041): Inferred latch for "x[0]" at comp4.v(210)
Info (10041): Inferred latch for "x[1]" at comp4.v(210)
Info (10041): Inferred latch for "x[2]" at comp4.v(210)
Info (10041): Inferred latch for "x[3]" at comp4.v(210)
Info (10041): Inferred latch for "x[4]" at comp4.v(210)
Info (10041): Inferred latch for "x[5]" at comp4.v(210)
Info (10041): Inferred latch for "x[6]" at comp4.v(210)
Info (10041): Inferred latch for "x[7]" at comp4.v(210)
Info: Elaborating entity "alu" for hierarchy "alu:alu1"
Warning (10235): Verilog HDL Always Construct warning at comp4.v(244): variable "x" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(244): variable "y" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at comp4.v(241): inferring latch(es) for variable "Alu_out", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "Alu_out[0]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[1]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[2]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[3]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[4]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[5]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[6]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[7]" at comp4.v(241)
Info: Elaborating entity "controller" for hierarchy "controller:controller1"
Warning (10230): Verilog HDL assignment warning at comp4.v(57): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(67): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(77): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(104): truncated value with size 32 to match size of target (4)
Warning: Net is missing source, defaulting to GND
Warning (12110): Net "Data_out[7]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[6]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[5]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[4]" is missing source, defaulting to GND
Warning: Net is missing source, defaulting to GND
Warning (12110): Net "Data_out[7]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[6]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[5]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[4]" is missing source, defaulting to GND
...
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 50 warnings