Verilog Syntax Q

[wuchy143]

Hi All,

I"m a little confused from the code below in reference to reset. What is it checking on reset? It is high? Or low?

if (~RESET) begin
q <= 1'b0;

 

[Mikebits]

Check this link out. See bitwise operators.
https://www.electro-tech-online.com/custompdfs/2010/05/lect2.pdf

 

[wuchy143]

Good link! Thx

So in context to what I was referring to the if statement is checking to see if RESET = 0. If it's true it then assigns a "0" to Q on the next clock cycle?

 

[BrownOut]

It does assign the value of zero to q, but not necessarily on the next clock cycle. If the code looks like this:

always@(posedge clock or reset)
if(~reset)
q <= 0;
...

Then the assignment is immediate and asychronous. If it looks like this:

always@(posedge clock)
if(~reset)
q<= 0;
...

then the reset values are assigned at the next clock.

 

[wuchy143]

Ok. So having that reset in there is making it happen on the next clock cycle? Hmmm I wonder why this is

 

[BrownOut]

Nope. Try reading my post again.

 

[wuchy143]

lol. oops. Sorry. I meant the opposite. Gotcha! Thanks