//4 to 1 mux using 2 to 1 muxs
module four_to_one(Y3,A,B,C,D,Sel,En);
input [3:0]A;
input [3:0]B;
input [3:0]C;
input [3:0]D;
input [1:0]Sel;
input En;
output [3:0]Y3;
reg [3:0]Y3;
Sel0 = Sel[0]; // line #17
Sel1 = Sel[1]; // line #18
two_to_1_mux mux1(Y1,A,B,Sel0,En);
two_to_1_mux mux2(Y2,C,D,Sel0,En);
two_to_1_mux mux3(Y3,Y1,Y2,Sel1,En);
endmodule
//stimulus
module testbench;
reg [3:0]A;
reg [3:0]B;
reg [3:0]C;
reg [3:0]D;
reg [1:0]Sel;
reg En;
wire [3:0]Y3;
four_to_one fourMux(Y3,A,B,C,D,Sel,En);
initial
begin
A<=4'b1111;
B<=4'b1010;
C<=4'b1100;
D<=4'b0011;
En<=1;
Sel=00;
#20 Sel=01;
#20 Sel=10;
#20 Sel=11;
#20 $finish;
end
endmodule