// Clock
module clock_10();
integer clk;
always begin
clk = 0;
#10 clk = 1;
#10;
end
endmodule
//D Flip-Flop
module D_flip_flop(Q_out,D_data,clk);
input clk;
input D_data;
output Q_out;
reg Q_out;
always @(posedge clk) begin
Q_out <= D_data;
end
endmodule
// Stimulus
module testbench;
reg D_data;
reg clk;
wire Q_out;
D_flip_flop d_flip_flop(Q_out,D_data,clk);
clock_10 clk; //line #47
initial
begin
D_data <= 1;
#25 D_data <= 0;
#45 D_data <= 1;
#65 D_data <= 0;
#50 $finish;
end
endmodule