vhdl help...

[abilash]

i hav written vhdl code in modules... i need to combine them.... any one of them should work depending on the bit pattern such as

when (signal = 00) => program 1;
when (signal = 01) => program 2;
when (signal = 10) => program 3;
when (signal = 11) => program 4;


how can i do this... plz help...

 

[tkbits]

You don't execute modules (entities), you create components (objects) from them. Then you connect signals.

-- create "enable" signals
en0 <= '1' when sig = 0 else '0';
en1 <= '1' when sig = 1 else '0';
en2 <= '1' when sig = 2 else '0';
en3 <= '1' when sig = 3 else '0';

-- create components
-- connect architecture "enable" signals to
--    component entity "enable" input signals
U_MOD0: entity mod0 port map(en => en0, ...);
U_MOD1: entity mod1 port map(en => en1, ...);
U_MOD2: entity mod2 port map(en => en2, ...);
U_MOD3: entity mod3 port map(en => en3, ...);

 

[Papabravo]

We are all just wasting our breath with this guy. It is so manifestly obvious that he is approaching VHDL as if it were a procedural language for implementing algorithms. He does not seem to get the idea that VHDL is a description language, the purpose of which is to synthesize a device to replicate the bahavior.

 

[Analog]

We are all just wasting our breath with this guy. It is so manifestly obvious that he is approaching VHDL as if it were a procedural language for implementing algorithms. He does not seem to get the idea that VHDL is a description language, the purpose of which is to synthesize a device to replicate the bahavior.

There are many good tutorial sites out there on this.

 

[Papabravo]

There are many good tutorial sites out there on this.

We know this. We've told him this. He should know this. Yet he keeps asking the same question with the same kind of example. It's almost as though an evil gnome keeps feeding him the same question over and over and orver.....

 

[gauravjindal]

tell me about any vhdl complex project till 4 dec..2009