I am glad I joined this forum because it seems there are a lot of knowledgeable people here.
However, my question still remains unanswered. I still don't understand the use of a dual decade counter over a decade counter. Namely, there are two clock inputs for each 4 bit output. When I read the specs on this chip, it is extremely vague about what each clock input is doing. I am still fairly new to the ttl world so that may have something to do with it.
The chip in question is a dual decade counter / divider. What that really means and you can see in the data sheet is we have two decade counters in a single package. Doing this with circuits is common. We can have 1, 2 or even 4 operational amplifiers in a single case (package) or for example a 555 timer is a single timer but a 556 is actually two 555 timers in a single package.
Back to the chip at hand. Depending on how a single decade counter is built it can divide. In the case of this chip, using half the chip, a single decade counter, it can divide a clock by 2, 4, 5 or 10. Since it is a dual decade counter we can now divide by 2, 4, 5, 10,
20, 25, 50 or 100 as covered in the data sheet. That is the advantage of two counters in a single package. Less space used.
This particular counter is what is called a "ripple" counter. Drop a pebble in the center of a pan of water. Note how the ripples travel.
Counters are a collection of flip flop circuits in this case. Each flip flop has two states, it is a 0 or 1.
Give this link a read to understand using flip flop circuits to count. Note where it talks about Asynchronous (ripple) counters to understand the ripple effect. That should help.
So what you have is just two counters in a single package. If I want to divide a clock down by 100 it is simpler to use one chip rather than two divide by ten chips.
Does that help?
Ron