What is Explicit Instantiation in Verilog

Hello All,

I'm having trouble figuring out what it means to explicitly instantiate in verilog. Could anyone give me a "seat of the pants" description...an example..or anything? After looking online for a while I just get more confused.

Regards,

-mike

Instantiation just refers to a hierartical design, where sub modules are connected to parent modules. Explicit can mean many different things. It probably refers to the way the pin connections are defined in the actual instantiation, all sub-module pins are named, as opposed to an instantiation that uses pin order to connect to the sub module pins. For example:

Explicit:

my_sub_module inst_my_sub_module
( .sub_clock (top_clock),
.sub_reset (top_reset),
...);

Position:
my_sub_module inst_my_sub_module
( top_clock,
top_reset,
...);

After thinking about it, I may have steered you wrong on the terminology. The examples I gave should be called "named" and "positional" Honestly, I don't think there is such a thing as explicit and implicit instantiations in verlog. In VHDL, however, there are.

You may be talking about the difference between 'instantiation' and 'inference'-
Instantiation makes a construct explicit, like so:
... in this case, the target has a hardware-multiplier, and we want to use it.

Inference, though, just specifies the re3sult, without specifying a method

In this case, the compiler uses a 'default' multiplier. This makes the code portable to architectures that do not have the 'hardware_multiplier' of tre first example.

hmmm. I'm a little confused. I'm quite a noob and perhaps I didn't give you guys enough information. Sorry. I guess putting it into a better context will help.

My mentor and stepdad(35 years experience in EE) has been giving me projects to get up to speed on FPGA's to start using them where I work as a hardware engineer. The second project he gave me came with a bunch of code to hopefully get me to a point where I can open up hyperterminal on my PC and send the FPGA commands and have it echo them back to me. He and a co-worker of his wrote most of the code but left some portions for me to do as a learning experience. In the write up he gave me it says to, "Explicitly instantiate I/O buffers which are unique to the manufacturer you are using, in this case Xilinx." I"m really just trying to understand the write up so I know what it wants me to do. I'm probably making a mountain out of a mole hill but I truly just want to understand all of this stuff to a T.

Considering the context, I think Wade hit the nail on the head in post #4. I/O buffers can be inferred as just the top-level ports in the design, or can be explicitly designated by creating modules to describe the ports. Look in the Xilinx documentation to see how this is done. Most often, the specifications for the port comes from the .UCF file that you already have some exposure to. However, you code can specify other things, like fast I/O regesters (by directives on your code). The Xilinx manuals should have all the information you need to do this.

PS: Don't feel bad about being confused. This is a rather advance topic, and I think you're advisor is getting a little ahead of you. Hope he doesn't want to beat me up for saying that

thx again brownout and others for the direction! Looks like I got some reading to do tonight

haha just read the P.S. Yeh. He's definitely getting ahead of me a little but I'm trying to get things at all angles to somewhat make up for that. I"m reading stuff on just verilog. Then I brush up a little on my digital knowledge I learned from school...play with my dev. board...and come on here! It's an advanced topic which I regret not getting into while in college. Plus it being hard just makes it that much more rewarding to understand and use. Cheers!

-mike