What means this..(easy question)

[TKS]

If the clock and data lines are both high the keyboard sends the (0) start bit, 8 data
bits, the parity bit and the stop bit. Data will be valid before the trailing edge and
beyond the leading edge of the clock pulse.

Tks?

 

[evandude]

I think that's a pretty clear description, depending on what you are asking... speaking of which... what are you asking?

 

[tkbits]

Sounds like PS/2.

When the keyboard is ready to send data, it will wait, if necessary, for both the clock and data lines to go high. Then it will send the given bit sequence.

A timing diagram will show how the bits are sent, and their relationship to the clock signal.

 

[TKS]

yeah fooks

really clever,

but i'm not an electronic student an i have all the stuff what i know home learnd..

Sow what i need to now is, do i need to capture the data line status when clock is high or when its low?

its just an bit of english words../confusion..

Tks

 

[evandude]

this site has a ton of great info on the PS/2 protocol:
**broken link removed**

taken from that site:
"The keyboard/mouse writes a bit on the Data line when Clock is high, and it is read by the host when Clock is low."