What's the function of these caps and resistors please?

Most of these LF amps either have a means of detecting a drive signal prior to the 74F74 or its equivalent flip flop and in the case of it disappearing stopping any signal from it to the driver IC to stop a FET being held shorted by the output transformer. If they don't have this function, like the above, they use capacitive coupling between the driver and the gates. This one is the only one I have seen where the capacitive coupling is before the driver chip, and from what you gents have said, it is also a time constant to help stop both pairs conducting. I think this is what Eric is saying in post #19 ??

Would you guys be OK if I posted a link to a zip file showing a series of scope shots showing how the drive signal decays at the end of a transmission sequence? I had my digital USB scope on single capture, and as I can't scroll an image I scrolled and took multiple screen shots. I believe this decaying signal showing the 2 gate waveforms may be what is causing a FET to pop every now and again.

Thanks.

hi,
You can post a zip file to this thread.
E

Chris Wilson said:

Some great info, thanks. spec, I was asking about C1 and C2, but thanks for the info re gate capacitance. I am also aware that with paralleled devices the driver has to work twice as hard, I believe?

Eric, thanks for the revised simulation, again, appreciated!

Tony, I have just tied the shutdown pin 11 to ground with a 10k. Thanks. I also tried two off 470 Ohms resistors between the 5V pins 1, 4 and 14 and pins 2 and 6 and pin 5. With power applied and no signal I saw circa 5V on the pin 5 side of one resistor, and less than 1V on the pins 2 and 6 side of the other 470 Ohms resistor. Feeding a signal in saw noisy gate and drain waveforms compared to no pull ups. My issue with this is when a signal stops I often get a blown FET, sometimes, but very very rarely, I get it when a signal starts. The input waveform when looked at with a single shot on the scope, doesn't start clean, it "stutters" into life, but I don't have much if any control as it originates in my commercially made transceiver....

Ideas welcome, it's at times like this thermionic tubes seem appealing

Click to expand...

IN FUTURE Please markup your schematic and show levels and waveforms of input and outputs. Inadequate info leads to our wasted time.
1V on the pins 2 with 470Ohm to 5V indicates an improvement with 4V rising edge swing but 20% rise above 0V indicates Zol= 125 Ohm which is not 75F but rather CMOS HC74. Did you substitute?

How can you expect an analysis without an accurate schematic?

Signal Integrity is critical in this design.

This is why you run into problems .

Chris Wilson said:

. This one is the only one I have seen where the capacitive coupling is before the driver chip, and from what you gents have said, it is also a time constant to help stop both pairs conducting. I think this is what Eric is saying in post #19 ??

Click to expand...

As I said before, the C and R differentiator will not stop both NMOSFET pairs turning on at the same time at the signal switching rate which has been implied in this thread. The reason for this is that the time constant of the differentiators is long compared to the period of the switching signal.

The simulation in post #6 shows differential action but it does not show what is happening in the actual circuit. In the simulation the period of the signal is shown as 30 micro seconds (half period 15uS), but as the frequency of the actual signal is 136KHz, this gives a period of 7.3 microseconds (half period 3.65 microseconds). The differentiator time constant is 1nF * 15K Ohms = 15 microseconds which is long compared to the 3.65 microsecond signal half period. Thus, the waveform will not be differentiated as shown in the simulation. Instead it will essentially be a square wave.

But the R/C diffrentiator will turn off both NMOSFET pairs if the input signal is absent. This has not been mentioned until post #16.

It is important to separate the circuit conditions with a normal switching signal and when the switching signal is absent, possibly at turn on.

spec

(I am not sure what Eric is saying in post #19. I have asked for an elaboration but, so far no response. I see Tony Stewart has agreed with the statement so perhaps he could help out)

spec. I would agree if the FF was CMOS, but the original design was TTL, so the time constants would be much shorter with a peak signal just above threshold. This design must change C values for a 5 V signal to reduce the period. as I indicated in post #12. I am not sure that Chris understands how to do this yet based on actions so far. Eric's simulation is fine for CMOS but the thresholds and RC times need tweaking for next stage, so incomplete.

Tony Stewart said:

spec. I would agree if the FF was CMOS, but the original design was TTL, so the time constants would be much shorter with a peak signal just above threshold. This design must change C values for a 5 V signal to reduce the period. as I indicated in post #12. I am not sure that Chris understands how to do this yet based on actions so far. Eric's simulation is fine for CMOS but the thresholds and RC times need tweaking for next stage, so incomplete.

Click to expand...

Thanks Tony, I see the reasoning but it has not gelled with me. I will give it some thought.

spec

The simulation in post #6 shows differential action but it does not show what is happening in the actual circuit. In the simulation the period of the signal is shown as 30 micro seconds (half period 15uS), but as the frequency of the actual signal is 136KHz, this gives a period of 7.3 microseconds (half period 3.65 microseconds). The differentiator time constant is 1nF * 15K Ohms = 15 microseconds which is long compared to the 3.65 microsecond signal half period. Thus, the waveform will not be differentiated as shown in the simulation. Instead it will essentially be a square wave.

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If you look at the IR2110 d/s you will see that the signal inputs have pull down resistors, in parallel with the 15k's.
I chose an arbitrary 10k to emphasis the differentiation.

The OP replied to my image plot:

OK, thanks a lot for taking the time and trouble to simulate this, I just had a look on my scope at the inputs to the driver and there's a good similarity in the traces, I am impressed!

Click to expand...

The OP did ask this question:
What's the function of these caps and resistors please?

E

Wow, you have opened up a can of worms Tony!

Going by the data sheets of the 74F74 and the IR2110 the 74F74 is not capable of driving the IR2110 worst case.

The 74F74 output logic 1 is only guaranteed to be 2.7V and the input threshold of the IR2110 is around 3.9V with a VCC of 5V.

The plot thickens

spec

ericgibbs said:

The OP replied to my image plot:

Click to expand...

?

ericgibbs said:

The OP did ask this question:
What's the function of these caps and resistors please?

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We are quite aware of that Eric and that is what has been discussed throughout this thread, apart from my error in post # 13, which is related to output transistor overlap though.

But, the OP also made other statements. And now it turns out that he is concerned that the output MOSFETs are blowing, which I would assume is the core reason for the original post.

You must accept that there are many aspects to circuit analysis and the important thing is to establish the facts.

spec

ericgibbs said:

If you look at the IR2110 d/s you will see that the signal inputs have pull down resistors, in parallel with the 15k's.
I chose an arbitrary 10k to emphasis the differentiation.

Click to expand...

10K pull downs is one hell of an assumption Eric.

spec

spec said:

10K pull downs is one hell of an assumption Eric.

Click to expand...

Read the post: I chose an arbitrary 10k to emphasis the differentiation.

My simulation was to answer the OP's question, it was not an invitation to you to troll.

Also ref post #19,
its a Bistable 7474, the Set and Reset pins are not used, tied High, so either the Q or /Q outputs could be Set high on power up.
Is that clear enough for you.?

Just to say I am not ignoring this, I am tied up with a load of work, and this stuff is a hobby, so has to take a back seat I am sorry to say! I am grateful to all who have posted and apologise if I have been unclear, or have not given correct / enough information, but do bear in mind I am a real beginner with electronics and am merely working to designs created by others whom I have to assume know what they are doing Tony: Please clarify in the simplest terms what info you need or what info I have not given accurately, I am perplexed. I will later give a brief resume of what i am trying to do and the problem I am having, to tie this all together. Thanks again all.

ericgibbs said:

Read the post: I chose an arbitrary 10k to emphasis the differentiation.

My simulation was to answer the OP's question, it was not an invitation to you to troll.

Also ref post #19,
its a Bistable 7474, the Set and Reset pins are not used, tied High, so either the Q or /Q outputs could be Set high on power up.
Is that clear enough for you.?

Click to expand...

Try and leave the personal stuff out Eric and stop arguing by making sweeping unfounded statements. Stick to technical matters. There is no trolling. Also try and be objective. This is not about you or me. It is about defining what the circuit function is.

I fully understand that a bistable will be in two states- it is obvious.

But the point you are not understanding/accepting is that whatever state the bi stable is in, without the capacitor coupling, one of the output transistor pairs will be turned on and if that state lasts for a certain time the current will build in the transformer and MOSFETs to a detrimental level.

It is not valid to assume that the pull down is 10K and that is why your simulation may not be valid.

Update 2017_02_24. In fact, the with a logic 1 input to the IR2110 the maximum current is 40 uA and the minimum logic level 1 is 9.5V, so the minimum value of the pull down (if it is a resistor) is 9.5/40 uA = 237.5K Ohms. The average figure is 20uA giving a pull down resistor value of 475K Ohms

spec

Chris Wilson

hi Chris,
From the simulation I have posted, together with the supporting text and the close comparison you have seen of the actual waveforms on your scope.

Do you have sufficient information to answer your original query regarding the function of the caps and and resistors that form that differentiation circuit.?

If not please ask and I will post more information.

Eric

Hi CW,

What was the shape of the waveform at the inputs to the gate driver? I would really like to know.

Could you draw it, or, better still, show a picture of your scope screen.

After analyzing the circuit, I come to the same conclusion as Tony Stewart in post #12 ( I missed his post unfortunately).

I think the core reason for your original post is that the output NMOSFETs are blowing from time to time. I would not be surprised if the output signal was also erratic/down on power for the reasons that Tony points out.

To be quite blunt, the approach to driving the inputs to the IR2110 is poor.

We can probably suggest some improvements though (as Tony has done), if that is what you want.

spec

I am "playing" tonight and will grab some scope shots. I have a 150MHz digital USB scope, and a Philips dual analogue / digital scope at 100 MHz. The USB one does of course lend itself better to posting screen shots direct from the PC. To me the gate waveforms look good and source ones not bad. I do indeed have the issue of FET's blowing, somewhat less than at one stage, but enough to be a PITA and costly. Most of the time (estimate 90% of the time) a failure comes at the end of a transmission cycle. I don't know if any here are into amateur radio, but I am using this to transmit digital signals on the 136kHz ham band. The amp is fed from a very low power output on my transceiver, about 1 dBm, into a pre amp to up the output enough to feed a frequency doubler. I have to do this as my transceiver is unable to generate a signal on 272 kHz. I need double the desired frequency as it's a push pull amp design and the output ends up half the frequency of the input. The digital signal is generated in software using a programme known as WSPR. Details are available here:

https://en.wikipedia.org/wiki/WSPR_(amateur_radio_software)

I need to be told whether I need to be looking at the input signal to the amp being the cause, as when a 2 minute transmission session ends, that's when a FET usually blows, and the input signal does "funny things" at the end of a sequence. I can only show it by using the scope in single shot mode, and then taking a screen shot of the captured data a screen full at a time as sequence of images. This is one idea I have as to the cause. The other is an issue with the pre amp or doubler circuit. I hope to finish a different exciter tonight which has the frequency doubling done in software and means I no longer need to use my transceiver, pre amp or doubler. This should prove whether any of those are the issue or not.

Finally two more ideas, I have to wonder if the output transformer is giving a back voltage to the FET's as a transmission stops, maybe due to saturation or whatever. I see spikes on the scope, but maybe it's induced into the scope probe leads, rather than "real"? I am not experienced enough to know if my methodology or equipment is to blame, or if the spikes are real. I run it off a computer server switch mode power supply that gives 50V at God knows how many amps, at 57 Amps I think. It's an HP ESP120 and it MAY have some noise on the output that's somehow getting into places it shouldn't. I very rarely have a FET failure running the amp off a 36V linear bench supply, but is that the lower voltage, or the cleaner supply? I just don't know...

So basically I need you experts to tell me what info is needed and how to get it, and i will try and provide it, should be interested in helping me. Thanks for reading and the help you have shared so far.

Hi CW, the plot thickens.

Can you state equivocally the frequency of the wave form feeding the inputs to the NMOSFET drivers. If that frequency is half the designed frequency of 136KHz and not pretty close to a 1: 1 mark to space ratio, you will have major problems.

Once we can arrive at the exact circuit conditions, as Tony Stewart indicated, we can then get down to sorting your problems. Even at 136 Khz there are a number of issues with the circuit as already stated.

spec

Unequivocally I am putting 137kHz X 2 into the 74F74 and seeing 137kHz on the gates and drains, which is correct. I attach waveforms from out of the transceiver, through the pre amp and doubler, at the input of the 74F74 IC, at the gates, and at the drains. For space / time I have only uploaded wave forms for one gate and one drain, but they are near as damn it all identical. This was done transmitting into the filter and antenna and being heard all over Europe. So working OK from that point of view..

Thanks, CW, can you also show the signal on the input to the PMOSFET driver?

spec

spec said:

Thanks, CW, can you also show the signal on the input to the PMOSFET driver?

spec

Click to expand...

Perhaps interestingly, no I cannot. With my cheap Chinese supposedly 200 MHz probe set X10 as in the other captures above, as soon as I probe on the driver chip side of either C1 or C2 the output goes wild, similar to how it goes if a FET is going to go bang, I will probe on the 74F74 sides of C1 and C2 and see what happens, fingers are crossed... Hmm that probes fine, and if I just touch the driver chip sides of C1 or C2 the signal goes wild. The capture should be attached, thanks very much spec!