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Where & how to block DC?

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atferrari

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My design of a DDS finally works OK but I want AC at the output. Block diagram attached.

My questions:

What is the correct place to get rid of the DC level?

A cap alone, is it the right way? If so, thinking of an output of 5Hz to 16 KHz what would be the right value?

Right now I have available non-polarized caps of 2uF and little space to parallel some.

What if I resort to an electrolytic or tantalum? How to know where the "+" terminal goes to?

Gracias for any help.
 
Just add a capacitor in series with the buffer input and a resistor to ground to provide a path for the input amp bias current. For a lower -3dB point of 1kHz and a 10k resistor, the cap size should be 16nF or larger. A standard ceramic cap would be fine for that.
 
Maybe at point (C)?

When testing this circuit I added the buffer at the input because the filter was loading somehow the signal generator (signal evidently distorted when entering the filter)

That is why I left it out as a possible point to insert the DC blocking cap.

Could I do it at point (C) where there is already a pot (10K)?

My signal goes from 5Hz to 16 KHz. Since I want up to 16 KHz passing un-attenuated, shouldn't I use a higher value for fc? Maybe some 19 KHz to say something? At lost here.

Edit / I understand we are talking of a HPF, right? Even more confused now. Sorry /

Thanks for your time Carl.
 
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Your filter is a Butterworth Lowpass Filter. A response curve shows no attenuation when the cutoff frequency is 1.33 to 1.5 times higher than your highest frequency.
 
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I want AC at the output.
Will the output swing both above and below ground (0V)? Do the op-amps have single or dual polarity supplies?
Could I do it at point (C) where there is already a pot (10K)?
You could. The optimum cap value needed would depend not only on the 10k but also on the values of the inverting-input resistor and the feedback resistor of the amplitude-control stage, but is likely to be at least 10uF to avoid significant attenuation at 5Hz.
What if I resort to an electrolytic or tantalum? How to know where the "+" terminal goes to?
That depends on the voltage bias of your opamp outputs and inputs, which aren't clear from a block diagram.
 
The schematic says the opamps are powered with plus and minus 9V. Then if the input swings above and below 0V then a coupling capacitor is not needed and the output will also swing above and below 0V.
 
Hi,


You schematic says 4v peak to peak, which is 2v peak which means the positive peak is +2v and the negative peak is -2v, unless it is offset with a dc voltage too. If it is offset then you might need a coupling capacitor.

The coupling capacitor should be a value large enough to pass the lowest frequency of operation, but because it looks like you're using a buffer you may find that it works better with some resistance from the buffer input to ground also. You might get away with 1megohom, but you may have to use 100k for lower noise.
 
Final (?) circuit

After revising my options I came to the attached circuit. 1uF and 100K seem to work OK.

In way of recalculating the filter (with higher fc) to have the last KHz unattenuated. Yes AudioGuru, you are right!

Gracias for replying.
 
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